{"id":10694,"date":"2026-07-20T10:11:44","date_gmt":"2026-07-20T10:11:44","guid":{"rendered":"https:\/\/ic-vendor.com\/cdclvc1104pwr\/"},"modified":"2026-07-20T10:11:44","modified_gmt":"2026-07-20T10:11:44","slug":"cdclvc1104pwr","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/ar\/cdclvc1104pwr\/","title":{"rendered":"CDCLVC1104PWR"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The CDCLVC1104PWR is a low-jitter 1:4 LVCMOS fan-out clock buffer from Texas Instruments, packaged in an 8-pin TSSOP (PW) package. It provides four LVCMOS output copies of a single LVCMOS input with an additive jitter of only 70 fs typical and output skew of less than 50 ps. The device operates from 2.5V or 3.3V supplies and supports frequencies up to 250 MHz at 3.3V.<\/p>\n

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\u0627\u0644\u0648\u0638\u064a\u0641\u0629<\/td>\n1:4 LVCMOS Fan-out Clock Buffer<\/td>\n<\/tr>\n
Fan-out Ratio<\/td>\n1:4<\/td>\n<\/tr>\n
Additive Jitter<\/td>\n70 fs (typical), < 100 fs<\/td>\n<\/tr>\n
Output Skew<\/td>\n< 50 ps (pin-to-pin)<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n2.5V or 3.3V<\/td>\n<\/tr>\n
Max Frequency<\/td>\n250 MHz (3.3V), 180 MHz (2.5V)<\/td>\n<\/tr>\n
Input\/Output<\/td>\nLVCMOS<\/td>\n<\/tr>\n
Output Enable<\/td>\nAsynchronous (1G pin)<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nTSSOP-8 (3.0 \u00d7 6.4 mm)<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n-40 \u062f\u0631\u062c\u0629 \u0645\u0626\u0648\u064a\u0629 \u0625\u0644\u0649 +85 \u062f\u0631\u062c\u0629 \u0645\u0626\u0648\u064a\u0629<\/td>\n<\/tr>\n<\/table>\n

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    \n
  • Ultra-low additive jitter: 70 fs typical for minimal timing degradation<\/li>\n
  • Low output skew: < 50 ps for tight clock alignment<\/li>\n
  • Pin-compatible family from 1:2 to 1:12 fan-out configurations<\/li>\n
  • Asynchronous output enable for flexible system control<\/li>\n
  • Supports 2.5V and 3.3V supply voltages<\/li>\n
  • Small 8-pin TSSOP package for space-constrained designs<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Clock tree fan-out in communication systems<\/li>\n
    • FPGA and processor clock distribution<\/li>\n
    • ADC\/DAC sample clock buffering<\/li>\n
    • Industrial control system clock trees<\/li>\n
    • Consumer electronics clock distribution<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CDCLVC1104PWR is a low-jitter 1:4 LVCMOS fan-out clock buffer from Texas Instruments, packaged in an 8-pin TSSOP (PW) package. It provides four LVCMOS output copies of a single LVCMOS input with an additive jitter of only 70 fs typical and output skew of less than 50 ps. The device operates from 2.5V […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[2035],"chip_brand":[138],"class_list":["post-10694","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","tag-cdclvc1104pwr","chip_brand-ti"],"acf":{"brief_explanation":"1:4 LVCMOS clock buffer, 70fs additive jitter, <50ps skew, 250MHz, TSSOP-8","date_code":"","package_case":"TSSOP-8 (3.0 \u00d7 6.4 \u00d7 1.05 mm)","in_stock":5278,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cdclvc1104.pdf","price":"$0.55 @ 1ku","product_introduction":"The CDCLVC1104 is a low-jitter, high-fan-out LVCMOS clock buffer that produces four identical copies of a single LVCMOS input clock. With additive jitter of only 70 fs typical and output skew below 50 ps, it preserves the timing integrity of precision clock sources throughout the distribution network. The device is part of a pin-compatible family ranging from 1:2 to 1:12 fan-out configurations, allowing designers to scale clock distribution without board layout changes. The LMK1C1104 is a newer pin-compatible version that also supports 1.8V supply operation with even lower jitter performance.","working_principle":"The CDCLVC1104 receives a single-ended LVCMOS clock input and distributes it to four identical LVCMOS output drivers through a carefully matched internal clock tree. The input buffer converts the LVCMOS signal to an internal logic level, which is then routed through symmetric metal traces to four output drivers. The matched trace lengths and balanced driver impedances ensure that all four outputs switch simultaneously within 50 ps of each other (output skew). The output enable (1G) pin provides asynchronous control to tri-state all outputs when de-asserted, allowing clock gating for power management. The low additive jitter is achieved through low-noise internal bias circuits and fast edge rates on the output drivers.","pin_description":"
      Pin<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>
      1<\/td>1G<\/td>Input<\/td>Output enable \u2014 active high, asynchronous<\/td><\/tr>
      2<\/td>1Y1<\/td>Output<\/td>Output 1 \u2014 LVCMOS clock copy<\/td><\/tr>
      3<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>
      4<\/td>1Y2<\/td>Output<\/td>Output 2 \u2014 LVCMOS clock copy<\/td><\/tr>
      5<\/td>1Y3<\/td>Output<\/td>Output 3 \u2014 LVCMOS clock copy<\/td><\/tr>
      6<\/td>VDD<\/td>Power<\/td>Supply (2.5V or 3.3V)<\/td><\/tr>
      7<\/td>1Y4<\/td>Output<\/td>Output 4 \u2014 LVCMOS clock copy<\/td><\/tr>
      8<\/td>1A<\/td>Input<\/td>LVCMOS clock input<\/td><\/tr><\/table>","application_scenarios":"
      • FPGA system clock fan-out to multiple peripherals and clock domains<\/li>
      • High-speed ADC\/DAC sample clock distribution to data converters<\/li>
      • Processor and SoC reference clock buffering in server platforms<\/li>
      • Industrial PLC clock tree distribution across multiple I\/O modules<\/li>
      • Video timing generator clock fan-out in broadcast equipment<\/li><\/ul>","alternative_models":"
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>
        TI<\/td>LMK1C1104PWR<\/td>TSSOP-8<\/td>Newer, 1.8\/2.5\/3.3V, lower jitter<\/td><\/tr>
        TI<\/td>CDCLVC1106PWR<\/td>TSSOP-8<\/td>1:6 fan-out variant<\/td><\/tr>
        Renesas<\/td>8SLVP1208<\/td>TSSOP-8<\/td>1:2 LVCMOS fan-out buffer<\/td><\/tr>
        Microchip<\/td>SY89873U<\/td>SOIC-8<\/td>1:4 LVDS\/CMOS fan-out<\/td><\/tr>
        onsemi<\/td>MC100LVEP14<\/td>SOIC-8<\/td>1:4 PECL fan-out<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/10694","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/comments?post=10694"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/10694\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/media?parent=10694"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/categories?post=10694"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/tags?post=10694"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=10694"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}