{"id":11628,"date":"2026-07-26T12:52:12","date_gmt":"2026-07-26T12:52:12","guid":{"rendered":"https:\/\/ic-vendor.com\/m95256-wmn6tp\/"},"modified":"2026-07-26T12:52:12","modified_gmt":"2026-07-26T12:52:12","slug":"m95256-wmn6tp","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/ar\/m95256-wmn6tp\/","title":{"rendered":"M95256-WMN6TP"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The M95256-WMN6TP from ST is a 256Kbit SPI serial EEPROM organized as 32Kx8. 20MHz SPI clock. 1M cycle endurance with 50-year data retention. 1.8V-5.5V wide supply range. Status register with block protection. TSSOP-8 package. Tape and reel.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n\n\n
\u0627\u0644\u0646\u0648\u0639<\/td>\n256 Kbit Serial EEPROM<\/td>\n<\/tr>\n
\u0627\u0644\u0643\u062b\u0627\u0641\u0629<\/td>\n256 Kbit (32K x 8)<\/td>\n<\/tr>\n
\u0627\u0644\u0648\u0627\u062c\u0647\u0629<\/td>\nSPI (up to 20 MHz)<\/td>\n<\/tr>\n
Write Time<\/td>\n5 ms max<\/td>\n<\/tr>\n
Endurance<\/td>\n1M erase\/write cycles<\/td>\n<\/tr>\n
\u0627\u0644\u0627\u062d\u062a\u0641\u0627\u0638 \u0628\u0627\u0644\u0628\u064a\u0627\u0646\u0627\u062a<\/td>\n50 years<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n1.8V to 5.5V<\/td>\n<\/tr>\n
Operating Temp<\/td>\n-40 to +85C<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nTSSOP-8<\/td>\n<\/tr>\n<\/table>\n

\u0645\u0628\u062f\u0623 \u0627\u0644\u0639\u0645\u0644<\/h2>\n

The M95256 uses a 256Kbit EEPROM array accessed through an SPI interface (SI, SO, SCK, CS). Instructions include READ, WRITE, WREN (write enable), WRDI (write disable), and RDSR\/WRSR (read\/write status register). The status register configures block protection areas (BP0, BP1) that prevent writes to protected memory regions. Page write operation writes up to 64 bytes in a single command. The write-in-progress (WIP) bit in the status register allows polling for write completion. HOLD pin suspends communication without resetting the serial sequence.<\/p>\n

\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
    \n
  • Parameter storage<\/li>\n
  • Configuration data<\/li>\n
  • User settings<\/li>\n
  • Calibration data<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

    Product Overview The M95256-WMN6TP from ST is a 256Kbit SPI serial EEPROM organized as 32Kx8. 20MHz SPI clock. 1M cycle endurance with 50-year data retention. 1.8V-5.5V wide supply range. Status register with block protection. TSSOP-8 package. Tape and reel. Key Specifications Type 256 Kbit Serial EEPROM Density 256 Kbit (32K x 8) Interface SPI (up […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[2904],"chip_brand":[142],"class_list":["post-11628","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","tag-m95256-wmn6tp","chip_brand-st"],"acf":{"brief_explanation":"M95256-WMN6TP - Serial EEPROM","date_code":"","package_case":"TSSOP-8 (3x4.4mm)","in_stock":4208,"datasheet":"https:\/\/www.st.com\/resource\/en\/datasheet\/m95256.pdf","price":"$0.70 @ 1ku","product_introduction":"The M95256-WMN6TP from ST is a 256Kbit SPI serial EEPROM organized as 32Kx8. 20MHz SPI clock. 1M cycle endurance with 50-year data retention. 1.8V-5.5V wide supply range. Status register with block protection. TSSOP-8 package. Tape and reel.","working_principle":"The M95256 uses a 256Kbit EEPROM array accessed through an SPI interface (SI, SO, SCK, CS). Instructions include READ, WRITE, WREN (write enable), WRDI (write disable), and RDSR\/WRSR (read\/write status register). The status register configures block protection areas (BP0, BP1) that prevent writes to protected memory regions. Page write operation writes up to 64 bytes in a single command. The write-in-progress (WIP) bit in the status register allows polling for write completion. HOLD pin suspends communication without resetting the serial sequence.","pin_description":"
    Pin<\/th>Name<\/th>Desc<\/th><\/tr>
    1<\/td>S<\/td>Chip select<\/td><\/tr>
    2<\/td>Q<\/td>Serial output<\/td><\/tr>
    3<\/td>D<\/td>Serial input<\/td><\/tr>
    4<\/td>VSS<\/td>Ground<\/td><\/tr>
    5<\/td>HOLD<\/td>Hold input<\/td><\/tr>
    6<\/td>C<\/td>Serial clock<\/td><\/tr>
    7<\/td>W<\/td>Write protect<\/td><\/tr>
    8<\/td>VCC<\/td>Supply<\/td><\/tr><\/table>","application_scenarios":"
    • Parameter storage<\/li>
    • Configuration data<\/li>
    • User settings<\/li>
    • Calibration data<\/li><\/ul>","alternative_models":"
      Model<\/th>Vendor<\/th>Diff<\/th><\/tr>
      M95128-WMN6TP<\/td>ST<\/td>128Kbit<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11628","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/comments?post=11628"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11628\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/media?parent=11628"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/categories?post=11628"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/tags?post=11628"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=11628"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}