{"id":11706,"date":"2026-07-26T14:04:21","date_gmt":"2026-07-26T14:04:21","guid":{"rendered":"https:\/\/ic-vendor.com\/74hc273d653\/"},"modified":"2026-07-27T10:15:22","modified_gmt":"2026-07-27T10:15:22","slug":"74hc273d653","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/ar\/74hc273d653\/","title":{"rendered":"74HC273D,653"},"content":{"rendered":"<h2>\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n<p>The 74HC273D,653 from Nexperia is an octal D-type edge-triggered flip-flop with active-low clear in a 20-pin SOIC package. Eight data inputs are clocked into the flip-flops on the rising edge of CLK, providing parallel data storage with synchronous output.<\/p>\n<h2>\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n<table>\n<tr>\n<td>\u0627\u0644\u0648\u0638\u064a\u0641\u0629<\/td>\n<td>Octal D-type flip-flop with clear<\/td>\n<\/tr>\n<tr>\n<td>\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n<td>2.0V to 6.0V<\/td>\n<\/tr>\n<tr>\n<td>\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n<td>14 ns at 5V<\/td>\n<\/tr>\n<tr>\n<td>Output Drive<\/td>\n<td>\u00b15.2 mA at 5V<\/td>\n<\/tr>\n<tr>\n<td>Trigger<\/td>\n<td>Rising edge<\/td>\n<\/tr>\n<tr>\n<td>\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\n<td>SOIC-20 (7.6&#215;10.3mm)<\/td>\n<\/tr>\n<\/table>\n<h2>\u0645\u0628\u062f\u0623 \u0627\u0644\u0639\u0645\u0644<\/h2>\n<p>On the rising edge of CLK, the D inputs are transferred to Q outputs. The active-low CLR input asynchronously clears all Q outputs to LOW regardless of CLK. This provides 8-bit parallel register functionality for data latching, address holding, and output staging in digital systems.<\/p>\n<h2>\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n<ul>\n<li>8-bit data register<\/li>\n<li>Address latch<\/li>\n<li>Output staging register<\/li>\n<li>State holding<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The 74HC273D,653 from Nexperia is an octal D-type edge-triggered flip-flop with active-low clear in a 20-pin SOIC package. Eight data inputs are clocked into the flip-flops on the rising edge of CLK, providing parallel data storage with synchronous output. Key Specifications Function Octal D-type flip-flop with clear Supply Voltage 2.0V to 6.0V Propagation [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[2986],"chip_brand":[140],"class_list":["post-11706","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","tag-74hc273d653","chip_brand-nexperia"],"acf":{"brief_explanation":"HC CMOS logic, 2-6V, high-speed","date_code":"","package_case":"SOIC-20","in_stock":13955,"datasheet":"https:\/\/www.nexperia.com\/products\/logic\/flip-flops-latches\/74HC273D","price":"$0.50 - $10.00","product_introduction":"The 74HC273D,653 from Nexperia is an octal D-type edge-triggered flip-flop with active-low clear in a 20-pin SOIC package. Eight data inputs are clocked into the flip-flops on the rising edge of CLK, providing parallel data storage with synchronous output.","working_principle":"On the rising edge of CLK, the D inputs are transferred to Q outputs. The active-low CLR input asynchronously clears all Q outputs to LOW regardless of CLK. This provides 8-bit parallel register functionality for data latching, address holding, and output staging in digital systems.","pin_description":"<table><tr><th>Pin<\/th><th>Name<\/th><th>Description<\/th><\/tr><tr><td>1<\/td><td>CLR<\/td><td>Master clear (active low)<\/td><\/tr><tr><td>2-9<\/td><td>Q1-Q8<\/td><td>Outputs<\/td><\/tr><tr><td>10<\/td><td>GND<\/td><td>Ground<\/td><\/tr><tr><td>11-18<\/td><td>D1-D8<\/td><td>Data inputs<\/td><\/tr><tr><td>19<\/td><td>CLK<\/td><td>Clock<\/td><\/tr><tr><td>20<\/td><td>VCC<\/td><td>Supply<\/td><\/tr><\/table>","application_scenarios":"<ul><li>8-bit data register<\/li><li>Address latch<\/li><li>Output staging register<\/li><li>State holding<\/li><\/ul>","alternative_models":"<table><tr><th>Model<\/th><th>Manufacturer<\/th><th>Key Difference<\/th><\/tr><tr><td>74HC374<\/td><td>Nexperia<\/td><td>Tri-state output version<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11706","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/comments?post=11706"}],"version-history":[{"count":1,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11706\/revisions"}],"predecessor-version":[{"id":12299,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11706\/revisions\/12299"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/media?parent=11706"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/categories?post=11706"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/tags?post=11706"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=11706"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}