{"id":11726,"date":"2026-07-26T14:04:48","date_gmt":"2026-07-26T14:04:48","guid":{"rendered":"https:\/\/ic-vendor.com\/cy8c3446lti-074\/"},"modified":"2026-07-27T10:01:04","modified_gmt":"2026-07-27T10:01:04","slug":"cy8c3446lti-074","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/ar\/cy8c3446lti-074\/","title":{"rendered":"CY8C3446LTI-074"},"content":{"rendered":"<h2>\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n<p>The CY8C3446LTI-074 from Infineon (Cypress) is a PSoC 3 programmable system-on-chip combining an 8051 core at 50 MHz with 24 universal digital blocks (UDBs), a delta-sigma ADC, PGAs, DACs, and comparators. It enables custom mixed-signal peripherals configured in hardware without RTL.<\/p>\n<h2>\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n<table>\n<tr>\n<td>\u0627\u0644\u0648\u0638\u064a\u0641\u0629<\/td>\n<td>PSoC 3 programmable system-on-chip<\/td>\n<\/tr>\n<tr>\n<td>\u0627\u0644\u0623\u0633\u0627\u0633\u064a\u0627\u062a<\/td>\n<td>8051 (up to 50 MHz)<\/td>\n<\/tr>\n<tr>\n<td>\u0641\u0644\u0627\u0634<\/td>\n<td>32 KB<\/td>\n<\/tr>\n<tr>\n<td>RAM<\/td>\n<td>2 KB + 1 KB EPACT<\/td>\n<\/tr>\n<tr>\n<td>UDBs<\/td>\n<td>24 universal digital blocks<\/td>\n<\/tr>\n<tr>\n<td>\u0627\u0644\u062a\u0646\u0627\u0638\u0631\u064a\u0629<\/td>\n<td>Delsigma ADC, PGA, comparator, DAC<\/td>\n<\/tr>\n<tr>\n<td>\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\n<td>TQFP-100 (14x14mm)<\/td>\n<\/tr>\n<\/table>\n<h2>\u0645\u0628\u062f\u0623 \u0627\u0644\u0639\u0645\u0644<\/h2>\n<p>The 8051 core runs application firmware. 24 UDBs implement custom digital peripherals (counters, PWM, UART, SPI, state machines) configured via PSoC Creator. Analog blocks include an 8-20 bit delta-sigma ADC, up to 4 PGAs, 4 voltage DACs, and 4 comparators with routing fabric. All analog and digital routing is configured at design time, eliminating external glue logic.<\/p>\n<h2>\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n<ul>\n<li>Custom mixed-signal peripheral<\/li>\n<li>Motor control with analog sense<\/li>\n<li>Sensor interface with PGA+ADC<\/li>\n<li>Industrial control<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The CY8C3446LTI-074 from Infineon (Cypress) is a PSoC 3 programmable system-on-chip combining an 8051 core at 50 MHz with 24 universal digital blocks (UDBs), a delta-sigma ADC, PGAs, DACs, and comparators. It enables custom mixed-signal peripherals configured in hardware without RTL. Key Specifications Function PSoC 3 programmable system-on-chip Core 8051 (up to 50 [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[3007],"chip_brand":[173],"class_list":["post-11726","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","tag-cy8c3446lti-074","chip_brand-infineon"],"acf":{"brief_explanation":"PSoC 3 programmable SoC, 8051 core @ 50MHz, 24 UDBs, delta-sigma ADC 8-20bit, 4 PGA, 4 DAC, 4 comparator, 32KB Flash, 2KB SRAM, TQFP-100","date_code":"074","package_case":"TQFP-100 (14x14mm)","in_stock":13046,"datasheet":"https:\/\/www.infineon.com\/dgdl\/Infineon-CY8C3446LTI-074-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7d0d8d47017d0dab0f0a0f0a","price":"$5.20 - $7.85","product_introduction":"The CY8C3446LTI-074 from Infineon (formerly Cypress) is a PSoC 3 programmable system-on-chip that integrates an enhanced 8051 core running at up to 50 MHz with 24 universal digital blocks (UDBs), a precision delta-sigma ADC (8-20 bit resolution), up to 4 programmable gain amplifiers (PGAs), 4 voltage DACs, and 4 comparators. Its unique architecture allows designers to create custom mixed-signal peripherals configured entirely in hardware through PSoC Creator IDE, eliminating the need for RTL coding or external glue logic. With 32 KB of on-chip Flash and 2 KB of SRAM, it is ideal for space-constrained embedded applications requiring flexible analog-digital integration.","working_principle":"The CY8C3446LTI-074 operates on the PSoC 3 architecture: an enhanced 8051 CPU core executes application firmware at up to 50 MHz, while the 24 Universal Digital Blocks (UDBs) \u2014 each combining two programmable logic macrocells (PLDs) with datapath elements \u2014 implement custom digital peripherals such as counters, PWMs, UARTs, SPI masters\/slaves, I2C, and arbitrary state machines, all configured graphically in PSoC Creator. On the analog side, the continuous-time blocks include up to 4 PGAs with configurable gain and input muxing, feeding a delta-sigma ADC with 8-bit to 20-bit programmable resolution and up to 8 single-ended or 4 differential channels. Four 8-bit voltage DACs provide analog output, and 4 high-speed comparators with programmable references enable rapid threshold detection. An analog routing fabric and digital interconnect matrix allow any analog or digital signal to be routed to any GPIO pin, providing unprecedented flexibility. Internal clock generation includes an IMO (internal main oscillator) at 24 MHz, PLL for higher frequencies, and optional external crystal support up to 33 MHz.","pin_description":"<table><tr><th>Pin Group<\/th><th>Pins<\/th><th>Name<\/th><th>Description<\/th><\/tr><tr><td>GPIO Port 0<\/td><td>P0[0]\u2013P0[6]<\/td><td>7 I\/O<\/td><td>Programmable GPIO with analog\/digital routing; ADC inputs, comparator inputs, DAC outputs<\/td><\/tr><tr><td>GPIO Port 1<\/td><td>P1[0]\u2013P1[6]<\/td><td>7 I\/O<\/td><td>Programmable GPIO with analog\/digital routing; PGA inputs\/outputs, comparator outputs<\/td><\/tr><tr><td>GPIO Port 2<\/td><td>P2[0]\u2013P2[6]<\/td><td>7 I\/O<\/td><td>Programmable GPIO with digital routing; PWM, UART, SPI signals<\/td><\/tr><tr><td>GPIO Port 3<\/td><td>P3[0]\u2013P3[6]<\/td><td>7 I\/O<\/td><td>Programmable GPIO with digital routing; Timer, counter outputs<\/td><\/tr><tr><td>GPIO Port 4<\/td><td>P4[0]\u2013P4[5]<\/td><td>6 I\/O<\/td><td>Programmable GPIO; additional digital peripheral routing<\/td><\/tr><tr><td>Power<\/td><td>VDD<\/td><td>4 pins<\/td><td>Digital\/analog supply voltage (1.8V\u20135.0V)<\/td><\/tr><tr><td>Ground<\/td><td>VSS<\/td><td>4 pins<\/td><td>Digital\/analog ground<\/td><\/tr><tr><td>Debug<\/td><td>SSCLK, SSDATA<\/td><td>2 pins<\/td><td>SWD (Single Wire Debug) programming and debug interface<\/td><\/tr><tr><td>Reset<\/td><td>XRES<\/td><td>1 pin<\/td><td>External active-low reset input<\/td><\/tr><tr><td>Crystal<\/td><td>XTAL_IN, XTAL_OUT<\/td><td>2 pins<\/td><td>External crystal oscillator (4\u201333 MHz)<\/td><\/tr><tr><td>Analog Ref<\/td><td>VREF<\/td><td>1 pin<\/td><td>External analog reference voltage input<\/td><\/tr><\/table>","application_scenarios":"<ul><li><b>Motor Control:<\/b> Multi-axis BLDC\/stepper motor drive with on-chip PGA for current sensing, delta-sigma ADC for position feedback, and UDB-configured PWM generation with dead-band insertion<\/li><li><b>Sensor Interface:<\/b> Industrial sensor signal conditioning chains (thermocouple, RTD, pressure) using PGA + 20-bit ADC for high-precision measurement without external instrumentation amplifiers<\/li><li><b>Capacitive Touch:<\/b> CapSense user interfaces with built-in CSD (capacitive sigma-delta) scanning algorithm, eliminating dedicated touch ICs<\/li><li><b>Power Management:<\/b> Digital power supply controllers implementing PID loops in UDB hardware with ADC feedback and DAC-driven PWM output<\/li><li><b>Custom Communication:<\/b> Niche protocol implementations (e.g., LIN, DMX512, 1-Wire) in UDB state machines without consuming CPU bandwidth<\/li><li><b>Industrial I\/O:<\/b> 4\u201320mA current loop transmitters\/receivers with on-chip DAC and comparator-based fault detection<\/li><\/ul>","alternative_models":"<table><tr><th>Model<\/th><th>Manufacturer<\/th><th>Core<\/th><th>Key Difference<\/th><\/tr><tr><td>CY8C5888LTI-LP097<\/td><td>Infineon<\/td><td>ARM Cortex-M3 @ 67MHz<\/td><td>PSoC 5LP with 32-bit ARM core, higher performance, more UDBs (24)<\/td><\/tr><tr><td>CY8C4248LTI-L489<\/td><td>Infineon<\/td><td>ARM Cortex-M0 @ 48MHz<\/td><td>PSoC 4 M-series, lower cost, fewer UDBs (4) but modern ARM core<\/td><\/tr><tr><td>CY8C3446AXI-084<\/td><td>Infineon<\/td><td>8051 @ 50MHz<\/td><td>Same PSoC 3 family, TQFP-100 but different speed grade and temp range<\/td><\/tr><tr><td>CY8C3866LTI-067<\/td><td>Infineon<\/td><td>8051 @ 50MHz<\/td><td>PSoC 3 with fewer UDBs (16), fewer analog blocks, lower cost option<\/td><\/tr><tr><td>CY8C6148AZI-S2F44<\/td><td>Infineon<\/td><td>ARM Cortex-M4 @ 150MHz<\/td><td>PSoC 6 dual-core (M4+M0), much higher performance with BLE 5.0<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11726","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/comments?post=11726"}],"version-history":[{"count":1,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11726\/revisions"}],"predecessor-version":[{"id":12004,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11726\/revisions\/12004"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/media?parent=11726"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/categories?post=11726"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/tags?post=11726"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=11726"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}