{"id":11996,"date":"2026-07-27T09:29:55","date_gmt":"2026-07-27T09:29:55","guid":{"rendered":"https:\/\/ic-vendor.com\/10cl120yf780c8g\/"},"modified":"2026-07-27T10:13:46","modified_gmt":"2026-07-27T10:13:46","slug":"10cl120yf780c8g","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/ar\/10cl120yf780c8g\/","title":{"rendered":"10CL120YF780C8G"},"content":{"rendered":"<h2>\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n<p>10CL120YF780C8G is an Intel Cyclone 10 LP 10CL120 FPGA, 120K LEs, 780-pin FBGA, commercial grade.<\/p>\n<h2>\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n<table>\n<tr>\n<td>\u0627\u0644\u0646\u0648\u0639<\/td>\n<td>Cyclone 10 LP FPGA<\/td>\n<\/tr>\n<tr>\n<td>Logic Elements<\/td>\n<td>119,088 LEs<\/td>\n<\/tr>\n<tr>\n<td>Embedded RAM<\/td>\n<td>3,981,312 bits<\/td>\n<\/tr>\n<tr>\n<td>Multipliers<\/td>\n<td>576 (18&#215;18)<\/td>\n<\/tr>\n<tr>\n<td>\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\n<td>780-pin FBGA (F780)<\/td>\n<\/tr>\n<tr>\n<td>Speed Grade<\/td>\n<td>C8<\/td>\n<\/tr>\n<tr>\n<td>Series<\/td>\n<td>10CL120<\/td>\n<\/tr>\n<\/table>\n<h2>\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n<ul>\n<li>119K LE Cyclone 10 LP FPGA<\/li>\n<li>3.98M bits embedded M9K RAM<\/li>\n<li>576 embedded 18&#215;18 multipliers<\/li>\n<li>Low-power cost-optimized<\/li>\n<\/ul>\n<h2>\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n<p>Refer to manufacturer datasheet for detailed application information and design guidelines.<\/p>","protected":false},"excerpt":{"rendered":"<p>Product Overview 10CL120YF780C8G is an Intel Cyclone 10 LP 10CL120 FPGA, 120K LEs, 780-pin FBGA, commercial grade. Key Specifications Type Cyclone 10 LP FPGA Logic Elements 119,088 LEs Embedded RAM 3,981,312 bits Multipliers 576 (18&#215;18) Package 780-pin FBGA (F780) Speed Grade C8 Series 10CL120 Features 119K LE Cyclone 10 LP FPGA 3.98M bits embedded M9K [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,22],"tags":[3290],"chip_brand":[2865],"class_list":["post-11996","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-video-ics","tag-10cl120yf780c8g","chip_brand-intel-altera"],"acf":{"brief_explanation":"Cyclone 10 LP FPGA, 119,088 LEs, M9K RAM, 18x18 multipliers, low-power cost-optimized","date_code":"8G","package_case":"780-pin FBGA","in_stock":10141,"datasheet":"https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/cyclone-10\/cyclone_10_lp_hb.pdf","price":"$3.50 - $85.00","product_introduction":"10CL120YF780C8G is an Intel Cyclone 10 LP 10CL120 FPGA, 120K LEs, 780-pin FBGA, commercial grade.","working_principle":"The 10CL120YF780C8G is a Cyclone 10 LP FPGA from Intel\/Altera. It uses a lookup table (LUT)-based fabric with configurable logic elements (LEs) that implement combinatorial and sequential logic. Embedded M9K\/M4K memory blocks provide on-chip RAM, ROM, and FIFO functions. Dedicated DSP multipliers accelerate arithmetic operations. A programmable interconnect matrix routes signals between logic, memory, and I\/O elements. Configuration is loaded from external flash or via JTAG\/AS programming. The device supports multiple I\/O standards including LVDS, SSTL, and HSTL for interfacing with diverse external devices.","pin_description":"<table><tr><th>Pin Group<\/th><th>Name<\/th><th>Description<\/th><\/tr><tr><td>I\/O<\/td><td>GPIO Banks<\/td><td>Programmable I\/O with multiple standard support (LVDS, SSTL, HSTL, LVCMOS)<\/td><\/tr><tr><td>Power<\/td><td>VCCIO, VCCINT, VCCPLL<\/td><td>Core, I\/O, and PLL supply voltages<\/td><\/tr><tr><td>Ground<\/td><td>GND<\/td><td>Ground reference<\/td><\/tr><tr><td>Config<\/td><td>DATA, DCLK, nCSO<\/td><td>JTAG\/AS\/AP configuration interface<\/td><\/tr><tr><td>Clock<\/td><td>CLK, PLL<\/td><td>Dedicated clock inputs and PLL feedback<\/td><\/tr><tr><td>Transceiver<\/td><td>TX\/RX (if applicable)<\/td><td>High-speed serial transceiver lanes<\/td><\/tr><\/table>","application_scenarios":"<ul><li>Digital signal processing and filtering<\/li><li>Custom protocol implementation (UART, SPI, I2C, PCIe)<\/li><li>Video and image processing pipelines<\/li><li>Motor control and industrial automation<\/li><li>Prototyping and glue logic integration<\/li><\/ul>","alternative_models":"<table><tr><th>Model<\/th><th>Manufacturer<\/th><th>Key Difference<\/th><\/tr><tr><td>XC7K325T<\/td><td>Xilinx<\/td><td>Kintex-7, 326K LE, Artix-class performance<\/td><\/tr><tr><td>ECP5-85<\/td><td>Lattice<\/td><td>84K LUT, low-cost mid-range alternative<\/td><\/tr><tr><td>iCE40HX8K<\/td><td>Lattice<\/td><td>8K LUT, ultra-low-cost small form factor<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11996","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/comments?post=11996"}],"version-history":[{"count":1,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11996\/revisions"}],"predecessor-version":[{"id":12012,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/11996\/revisions\/12012"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/media?parent=11996"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/categories?post=11996"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/tags?post=11996"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=11996"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}