{"id":7092,"date":"2026-06-23T03:36:47","date_gmt":"2026-06-23T03:36:47","guid":{"rendered":"https:\/\/ic-vendor.com\/74hct125d\/"},"modified":"2026-06-23T03:36:47","modified_gmt":"2026-06-23T03:36:47","slug":"74hct125d","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/ar\/74hct125d\/","title":{"rendered":"74HCT125D"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The 74HCT125D from Nexperia is a quad buffer\/line driver with 3-state outputs in SOIC-14. Each buffer has an active-low output enable, allowing bus-oriented applications where multiple devices share common data lines. HCT input levels provide compatibility with LSTTL while driving CMOS-level outputs.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n\n
\u0639\u0627\u0626\u0644\u0629 \u0627\u0644\u0645\u0646\u0637\u0642<\/td>\n74HCT<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n4.5 V to 5.5 V<\/td>\n<\/tr>\n
\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n13 ns (typ)<\/td>\n<\/tr>\n
\u062a\u064a\u0627\u0631 \u0627\u0644\u0625\u062e\u0631\u0627\u062c<\/td>\n+\/-6 mA<\/td>\n<\/tr>\n
Input Levels<\/td>\nLSTTL compatible (HCT)<\/td>\n<\/tr>\n
\u0627\u0644\u0642\u0646\u0648\u0627\u062a<\/td>\n4 (independent)<\/td>\n<\/tr>\n
Output Enable<\/td>\nActive low (per buffer)<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n-40C to +125C<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • Quad non-inverting buffer with individual 3-state output enables<\/li>\n
  • HCT input compatibility with LSTTL logic levels<\/li>\n
  • Active-low output enable per channel for bus sharing<\/li>\n
  • 13ns typical propagation delay for fast signal buffering<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Bus driver and buffer for microprocessor systems<\/li>\n
    • 3-state bus interface for shared data lines<\/li>\n
    • Level translation between TTL and CMOS<\/li>\n
    • Signal buffering and fan-out enhancement<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The 74HCT125D from Nexperia is a quad buffer\/line driver with 3-state outputs in SOIC-14. Each buffer has an active-low output enable, allowing bus-oriented applications where multiple devices share common data lines. HCT input levels provide compatibility with LSTTL while driving CMOS-level outputs. Key Specifications Logic Family 74HCT Supply Voltage 4.5 V to 5.5 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[],"chip_brand":[140],"class_list":["post-7092","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","chip_brand-nexperia"],"acf":{"brief_explanation":"Quad buffer\/line driver, 3-state, HCT, SOIC-14, 13ns, LSTTL compatible, bus driver","date_code":"","package_case":"SOIC-14 (8.65 x 3.91 x 1.58 mm)","in_stock":18200,"datasheet":"https:\/\/www.nexperia.com\/product\/74HCT125D","price":"$0.25 @ 1ku","product_introduction":"The 74HCT125D from Nexperia is a quad non-inverting buffer\/line driver with 3-state outputs in SOIC-14. Each of the four buffers has an independent active-low output enable (OE), allowing individual channel control for bus-oriented applications. The HCT input logic levels are compatible with LSTTL (VIH=2.0V, VIL=0.8V) while the outputs drive full CMOS levels at VCC. The device operates from 4.5V to 5.5V with 13ns typical propagation delay and +\/-6mA output drive current. When OE is high, the output enters high-impedance state, allowing bus sharing with other devices.","working_principle":"The 74HCT125D contains four independent non-inverting buffers with 3-state output control. (1) Buffer: Each buffer passes the input data to the output without inversion. The HCT input stage has TTL-compatible threshold (VIH=2.0V, VIL=0.8V), enabling direct interface with LSTTL outputs. The output stage drives full CMOS voltage levels. (2) 3-State Control: When the output enable (OE) pin is low, the buffer output is active and drives the data. When OE is high, both the pull-up and pull-down transistors in the output stage are turned off, placing the output in a high-impedance (Hi-Z) state. This allows multiple 3-state devices to share a common bus without contention. (3) Bus Sharing: Only one device should drive the bus at a time. The 13ns propagation delay and fast enable\/disable times allow efficient bus arbitration.","pin_description":"
      Pin<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>
      1<\/td>1OE<\/td>Input<\/td>Channel A output enable (active low)<\/td><\/tr>
      2<\/td>1A<\/td>Input<\/td>Channel A data input<\/td><\/tr>
      3<\/td>1Y<\/td>Output<\/td>Channel A output (3-state)<\/td><\/tr>
      4<\/td>2OE<\/td>Input<\/td>Channel B output enable (active low)<\/td><\/tr>
      5<\/td>2A<\/td>Input<\/td>Channel B data input<\/td><\/tr>
      6<\/td>2Y<\/td>Output<\/td>Channel B output (3-state)<\/td><\/tr>
      7<\/td>GND<\/td>Ground<\/td>Ground<\/td><\/tr>
      8-14<\/td>3Y\/3A\/3OE\/4Y\/4A\/4OE\/VCC<\/td>I\/O<\/td>Channels C, D, and power<\/td><\/tr><\/table>","application_scenarios":"
      • Microprocessor bus driver with 3-state output for shared data lines<\/li>
      • Level translation between TTL outputs and CMOS inputs<\/li>
      • Signal buffering and fan-out enhancement for clock and control signals<\/li>
      • I\/O port expansion with individual enable control<\/li><\/ul>","alternative_models":"
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>
        TI<\/td>SN74HCT125DR<\/td>SOIC-14<\/td>Direct equivalent<\/td><\/tr>
        onsemi<\/td>MC74HCT125ADG<\/td>SOIC-14<\/td>Direct equivalent<\/td><\/tr>
        Nexperia<\/td>74HC125D<\/td>SOIC-14<\/td>HC version, CMOS inputs<\/td><\/tr>
        Nexperia<\/td>74HCT126D<\/td>SOIC-14<\/td>Active-high enable version<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/7092","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/comments?post=7092"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/posts\/7092\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/media?parent=7092"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/categories?post=7092"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/tags?post=7092"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=7092"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}