{"id":10474,"date":"2026-07-20T04:13:27","date_gmt":"2026-07-20T04:13:27","guid":{"rendered":"https:\/\/ic-vendor.com\/74hc595d-3\/"},"modified":"2026-07-20T04:13:27","modified_gmt":"2026-07-20T04:13:27","slug":"74hc595d-3","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/es\/74hc595d-3\/","title":{"rendered":"74HC595D"},"content":{"rendered":"

Productos<\/h2>\n

The Nexperia 74HC595D is an 8-bit serial-in\/parallel-out shift register with output latches and 3-state outputs in an SO16 package. It operates from 2.0 V to 6.0 V, features a storage register with 3-state outputs, and supports cascading for expanding output ports via serial communication.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n
Supply Voltage (VCC)<\/td>\n2.0 V to 6.0 V<\/td>\n<\/tr>\n
Logic Family<\/td>\n74HC (CMOS)<\/td>\n<\/tr>\n
Shift Register Width<\/td>\n8 bits<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n25 MHz (at 4.5V)<\/td>\n<\/tr>\n
Output Type<\/td>\n3-state (via OE)<\/td>\n<\/tr>\n
Output Drive<\/td>\n\u00b15.2 mA<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n13 ns (typical at 4.5V)<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n-40\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n
ESD Protection<\/td>\nHBM >2000V, CDM >1000V<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • 8-bit serial-in parallel-out shift register with output latches<\/li>\n
  • 3-state outputs for bus-oriented applications<\/li>\n
  • Serial output for cascading multiple devices<\/li>\n
  • Direct clear (SRCLR) for shift register reset<\/li>\n
  • Wide supply voltage range from 2.0 V to 6.0 V<\/li>\n
  • CMOS low power dissipation with high noise immunity<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • LED display driver and multiplexing<\/li>\n
    • Serial-to-parallel data conversion<\/li>\n
    • Output port expansion for microcontrollers<\/li>\n
    • Cascaded display systems<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The Nexperia 74HC595D is an 8-bit serial-in\/parallel-out shift register with output latches and 3-state outputs in an SO16 package. It operates from 2.0 V to 6.0 V, features a storage register with 3-state outputs, and supports cascading for expanding output ports via serial communication. Key Specifications Supply Voltage (VCC) 2.0 V to 6.0 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[116],"chip_brand":[168],"class_list":["post-10474","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","tag-74hc595d","chip_brand-nxp"],"acf":{"brief_explanation":"8-bit serial-in\/parallel-out shift register with output latches, 3-state, 2.0-6.0V, SO16, cascading","date_code":"","package_case":"SO16 (SOT109-1) 10.0 x 3.9 x 1.75 mm","in_stock":12048,"datasheet":"https:\/\/assets.nexperia.com\/documents\/data-sheet\/74HC_HCT595.pdf","price":"$0.18 @ 1ku","product_introduction":"The Nexperia 74HC595D is an 8-bit serial-in parallel-out shift register with output latches and 3-state outputs in an SO16 package. The device contains an 8-bit shift register that feeds an 8-bit storage register. The shift register has a serial data input (SER), a serial output (Q7') for cascading, and a serial clock input (SRCLK). The storage register has a parallel 8-bit output and a storage clock input (RCLK). The active LOW output enable input (OE) controls the 3-state outputs. When OE is HIGH, the outputs are in a high-impedance state. The active LOW shift register clear (SRCLR) can reset the shift register independently of the storage register. The device operates from 2.0V to 6.0V with \u00b15.2 mA output drive and is specified from -40\u00b0C to +125\u00b0C.","working_principle":"The 74HC595D operates in two stages: a shift register and a storage register. Data is shifted into the 8-bit shift register on each rising edge of the shift clock (SRCLK) via the serial data input (SER). After 8 clock cycles, the shifted data can be transferred to the storage register by applying a rising edge to the storage clock (RCLK). This two-stage architecture allows new data to be shifted in while the previous data remains stable on the outputs. The serial output (Q7') provides the last bit of the shift register for cascading to subsequent 74HC595 devices. The active LOW output enable (OE) controls the 3-state output buffers \u2014 when HIGH, all outputs are high-impedance. The active LOW shift register clear (SRCLR) resets the shift register to all zeros without affecting the storage register. Multiple devices can be cascaded by connecting Q7' to the SER of the next device.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>\n
      1<\/td>Q1<\/td>Output<\/td>Storage register output bit 1<\/td><\/tr>\n
      2<\/td>Q2<\/td>Output<\/td>Storage register output bit 2<\/td><\/tr>\n
      3<\/td>Q3<\/td>Output<\/td>Storage register output bit 3<\/td><\/tr>\n
      4<\/td>Q4<\/td>Output<\/td>Storage register output bit 4<\/td><\/tr>\n
      5<\/td>Q5<\/td>Output<\/td>Storage register output bit 5<\/td><\/tr>\n
      6<\/td>Q6<\/td>Output<\/td>Storage register output bit 6<\/td><\/tr>\n
      7<\/td>Q7<\/td>Output<\/td>Storage register output bit 7<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground (0 V)<\/td><\/tr>\n
      9<\/td>Q7'<\/td>Output<\/td>Serial output from shift register (for cascading)<\/td><\/tr>\n
      10<\/td>SRCLR<\/td>Input<\/td>Shift register clear (active LOW)<\/td><\/tr>\n
      11<\/td>SRCLK<\/td>Input<\/td>Shift register clock input<\/td><\/tr>\n
      12<\/td>RCLK<\/td>Input<\/td>Storage register clock (latch) input<\/td><\/tr>\n
      13<\/td>OE<\/td>Input<\/td>Output enable input (active LOW, 3-state)<\/td><\/tr>\n
      14<\/td>SER<\/td>Input<\/td>Serial data input<\/td><\/tr>\n
      15<\/td>Q0<\/td>Output<\/td>Storage register output bit 0<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply voltage<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • LED matrix and 7-segment display driver circuits<\/li>\n
      • Serial-to-parallel data conversion in embedded systems<\/li>\n
      • Output port expansion for microcontrollers with limited GPIO<\/li>\n
      • Cascaded display systems for large LED panels<\/li>\n
      • Industrial control relay driver arrays<\/li>\n<\/ul>","alternative_models":"\n
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>\n
        Texas Instruments<\/td>SN74HC595D<\/td>SOIC-16<\/td>Pin-to-pin compatible<\/td><\/tr>\n
        onsemi<\/td>MC74HC595ADTR2G<\/td>TSSOP-16<\/td>Equivalent function<\/td><\/tr>\n
        Microchip<\/td>MM74HC595MTCX<\/td>TSSOP-16<\/td>Equivalent function<\/td><\/tr>\n
        Nexperia<\/td>74HCT595D<\/td>SO16<\/td>TTL input level variant<\/td><\/tr>\n
        Nexperia<\/td>74HC595PW<\/td>TSSOP16<\/td>Same function, TSSOP package<\/td><\/tr>\n<\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/posts\/10474","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/comments?post=10474"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/posts\/10474\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/media?parent=10474"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/categories?post=10474"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/tags?post=10474"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/chip_brand?post=10474"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}