{"id":11595,"date":"2026-07-26T12:50:55","date_gmt":"2026-07-26T12:50:55","guid":{"rendered":"https:\/\/ic-vendor.com\/epc2lc20n\/"},"modified":"2026-07-26T12:50:55","modified_gmt":"2026-07-26T12:50:55","slug":"epc2lc20n","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/es\/epc2lc20n\/","title":{"rendered":"EPC2LC20N"},"content":{"rendered":"<h2>Productos<\/h2>\n<p>The EPC2LC20N is an Intel\/Altera serial configuration device for FPGAs. 2Mbit density for storing configuration data for APEX, FLEX, and Cyclone FPGAs. Active Serial interface for single-FPGA configuration. JTAG in-system programmable. PLCC-20 package.<\/p>\n<h2>Especificaciones<\/h2>\n<table>\n<tr>\n<td>Tipo<\/td>\n<td>Serial Configuration Device (EPC2)<\/td>\n<\/tr>\n<tr>\n<td>Densidad<\/td>\n<td>1,705,984 bits (2 Mbit)<\/td>\n<\/tr>\n<tr>\n<td>Interface<\/td>\n<td>Active Serial (AS)<\/td>\n<\/tr>\n<tr>\n<td>Clock Frequency<\/td>\n<td>Up to 20 MHz (DCLK)<\/td>\n<\/tr>\n<tr>\n<td>Programming<\/td>\n<td>JTAG ISP<\/td>\n<\/tr>\n<tr>\n<td>Tensi\u00f3n de alimentaci\u00f3n<\/td>\n<td>3.3V<\/td>\n<\/tr>\n<tr>\n<td>Temperatura de funcionamiento<\/td>\n<td>0 to +70C (Commercial)<\/td>\n<\/tr>\n<tr>\n<td>Paquete<\/td>\n<td>PLCC-20<\/td>\n<\/tr>\n<\/table>\n<h2>Principio de funcionamiento<\/h2>\n<p>The EPC2 stores FPGA configuration bitstreams in non-volatile flash memory. On power-up, the EPC2 automatically clocks out the configuration data to the FPGA via the Active Serial (AS) interface using DCLK and DATA0 signals. The nCS pin selects the device; nCONF_DONE signals successful configuration. The EPC2 supports page mode for storing multiple configuration files. JTAG interface allows in-system programming of the flash memory without removing the device.<\/p>\n<h2>Aplicaciones<\/h2>\n<ul>\n<li>FPGA configuration storage<\/li>\n<li>Active Serial programming<\/li>\n<li>Multi-page configurations<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The EPC2LC20N is an Intel\/Altera serial configuration device for FPGAs. 2Mbit density for storing configuration data for APEX, FLEX, and Cyclone FPGAs. Active Serial interface for single-FPGA configuration. JTAG in-system programmable. PLCC-20 package. Key Specifications Type Serial Configuration Device (EPC2) Density 1,705,984 bits (2 Mbit) Interface Active Serial (AS) Clock Frequency Up to [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[2866],"chip_brand":[2865],"class_list":["post-11595","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","tag-epc2lc20n","chip_brand-intel-altera"],"acf":{"brief_explanation":"EPC2LC20N - FPGA Configuration Device","date_code":"","package_case":"PLCC-20","in_stock":9500,"datasheet":"https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/ds\/epc.pdf","price":"$3.50 @ 1ku","product_introduction":"The EPC2LC20N is an Intel\/Altera serial configuration device for FPGAs. 2Mbit density for storing configuration data for APEX, FLEX, and Cyclone FPGAs. Active Serial interface for single-FPGA configuration. JTAG in-system programmable. PLCC-20 package.","working_principle":"The EPC2 stores FPGA configuration bitstreams in non-volatile flash memory. On power-up, the EPC2 automatically clocks out the configuration data to the FPGA via the Active Serial (AS) interface using DCLK and DATA0 signals. The nCS pin selects the device; nCONF_DONE signals successful configuration. The EPC2 supports page mode for storing multiple configuration files. JTAG interface allows in-system programming of the flash memory without removing the device.","pin_description":"<table><tr><th>Pin<\/th><th>Name<\/th><th>Desc<\/th><\/tr><tr><td>DCLK<\/td><td>Clock<\/td><td>Serial clock output<\/td><\/tr><tr><td>DATA0<\/td><td>Data<\/td><td>Serial data output<\/td><\/tr><tr><td>nCS<\/td><td>Chip Select<\/td><td>Active low select<\/td><\/tr><tr><td>JTAG<\/td><td>TCK\/TDI\/TDO\/TMS<\/td><td>Programming<\/td><\/tr><\/table>","application_scenarios":"<ul><li>FPGA configuration storage<\/li><li>Active Serial programming<\/li><li>Multi-page configurations<\/li><\/ul>","alternative_models":"<table><tr><th>Model<\/th><th>Vendor<\/th><th>Diff<\/th><\/tr><tr><td>EPC4<\/td><td>Intel<\/td><td>4 Mbit<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/posts\/11595","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/comments?post=11595"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/posts\/11595\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/media?parent=11595"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/categories?post=11595"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/tags?post=11595"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/es\/wp-json\/wp\/v2\/chip_brand?post=11595"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}