{"id":10466,"date":"2026-07-20T04:09:45","date_gmt":"2026-07-20T04:09:45","guid":{"rendered":"https:\/\/ic-vendor.com\/74lvc2g74dc\/"},"modified":"2026-07-20T04:09:45","modified_gmt":"2026-07-20T04:09:45","slug":"74lvc2g74dc","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/zh\/74lvc2g74dc\/","title":{"rendered":"74LVC2G74DC"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The Nexperia 74LVC2G74DC is a single positive-edge triggered D-type flip-flop with set and reset, housed in a VSSOP8 package. It operates from 1.65 V to 5.5 V, offers \u00b132 mA output drive, 3.5 ns propagation delay, and features Schmitt-trigger inputs and Ioff circuitry for partial power-down mode.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n
Supply Voltage (VCC)<\/td>\n1.65 V \u81f3 5.5 V<\/td>\n<\/tr>\n
Propagation Delay (tpd)<\/td>\n3.5 ns (typical)<\/td>\n<\/tr>\n
Max Frequency<\/td>\n280 MHz<\/td>\n<\/tr>\n
Output Drive<\/td>\n\u00b132 mA<\/td>\n<\/tr>\n
\u8f93\u5165\u7c7b\u578b<\/td>\nSchmitt-trigger, 5V tolerant<\/td>\n<\/tr>\n
Logic Switching Levels<\/td>\nCMOS\/LVTTL<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive Edge<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n-40\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nVSSOP8 (SOT765-1)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Wide supply voltage range from 1.65 V to 5.5 V<\/li>\n
  • Overvoltage tolerant inputs up to 5.5 V<\/li>\n
  • Schmitt-trigger action at all inputs for slower rise\/fall tolerance<\/li>\n
  • Ioff circuitry enables partial power-down mode operation<\/li>\n
  • \u00b124 mA output drive at VCC = 3.0V (\u00b132 mA max)<\/li>\n
  • Latch-up performance exceeds 250 mA<\/li>\n
  • Complies with JEDEC standards JESD8-7, JESD8-5, JESD8-B<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Registers and data storage in portable devices<\/li>\n
    • Clock synchronization circuits<\/li>\n
    • Mixed 3.3V and 5V voltage translation<\/li>\n
    • Industrial control logic<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The Nexperia 74LVC2G74DC is a single positive-edge triggered D-type flip-flop with set and reset, housed in a VSSOP8 package. It operates from 1.65 V to 5.5 V, offers \u00b132 mA output drive, 3.5 ns propagation delay, and features Schmitt-trigger inputs and Ioff circuitry for partial power-down mode. Key Specifications Supply Voltage (VCC) 1.65 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[1772],"chip_brand":[168],"class_list":["post-10466","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","tag-74lvc2g74dc","chip_brand-nxp"],"acf":{"brief_explanation":"Single D-type flip-flop with set\/reset, positive edge trigger, 1.65-5.5V, VSSOP8, 3.5ns tpd, 280MHz","date_code":"","package_case":"VSSOP8 (SOT765-1) 2.3 x 2.0 x 0.75 mm","in_stock":5417,"datasheet":"https:\/\/assets.nexperia.com\/documents\/data-sheet\/74LVC2G74.pdf","price":"$0.23 @ 1ku","product_introduction":"The Nexperia 74LVC2G74DC is a single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. The device operates over a wide supply voltage range of 1.65 V to 5.5 V with inputs that can be driven from either 3.3 V or 5 V devices, enabling use as a translator in mixed-voltage environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. The Ioff circuitry disables the output during power-down, preventing damaging backflow current. The device is specified from -40\u00b0C to +125\u00b0C.","working_principle":"The 74LVC2G74DC implements a single D-type flip-flop with asynchronous set and reset. On the rising edge of the clock (CP), the data at the D input is sampled and transferred to the Q output. The set (SD, active LOW) and reset (RD, active LOW) inputs operate asynchronously and independently of the clock \u2014 asserting SD forces Q HIGH, while asserting RD forces Q LOW. When both SD and RD are deasserted (HIGH), normal clocked operation resumes. Schmitt-trigger input buffers on all inputs provide hysteresis for noise immunity and tolerance of slow input transitions. The Ioff circuitry ensures that when VCC is at 0V, all outputs are placed in a high-impedance state, preventing backflow current through the device \u2014 essential for partial power-down applications.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>\n
      1<\/td>CP<\/td>Input<\/td>Clock input (positive edge triggered)<\/td><\/tr>\n
      2<\/td>D<\/td>Input<\/td>Data input<\/td><\/tr>\n
      3<\/td>Q<\/td>Output<\/td>True output<\/td><\/tr>\n
      4<\/td>GND<\/td>Power<\/td>Ground (0 V)<\/td><\/tr>\n
      5<\/td>~Q<\/td>Output<\/td>Complementary output<\/td><\/tr>\n
      6<\/td>nRD<\/td>Input<\/td>Asynchronous reset (active LOW)<\/td><\/tr>\n
      7<\/td>nSD<\/td>Input<\/td>Asynchronous set (active LOW)<\/td><\/tr>\n
      8<\/td>VCC<\/td>Power<\/td>Supply voltage<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Data registers and storage in portable electronics<\/li>\n
      • Clock domain synchronization circuits<\/li>\n
      • Voltage level translation between 3.3V and 5V logic<\/li>\n
      • Industrial control and automation logic<\/li>\n
      • Automotive electronic control modules<\/li>\n<\/ul>","alternative_models":"\n
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>\n
        Texas Instruments<\/td>SN74LVC2G74DCUR<\/td>VSSOP-8<\/td>Pin-to-pin compatible<\/td><\/tr>\n
        onsemi<\/td>NL17SZ74USG<\/td>MicroPak-6<\/td>Single D flip-flop, smaller package<\/td><\/tr>\n
        Toshiba<\/td>TC7W74FK<\/td>USV-8<\/td>Equivalent function<\/td><\/tr>\n
        Nexperia<\/td>74LVC2G74DP<\/td>TSSOP8<\/td>Same function, TSSOP package<\/td><\/tr>\n
        Nexperia<\/td>74LVC1G74DC<\/td>VSSOP8<\/td>Similar single D flip-flop variant<\/td><\/tr>\n<\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts\/10466","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/comments?post=10466"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts\/10466\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/media?parent=10466"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/categories?post=10466"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/tags?post=10466"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=10466"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}