{"id":12333,"date":"2026-07-28T03:24:24","date_gmt":"2026-07-28T03:24:24","guid":{"rendered":"https:\/\/ic-vendor.com\/is61lv25616al-10tl\/"},"modified":"2026-07-28T03:24:24","modified_gmt":"2026-07-28T03:24:24","slug":"is61lv25616al-10tl","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/zh\/is61lv25616al-10tl\/","title":{"rendered":"IS61LV25616AL-10TL"},"content":{"rendered":"<h2>\u4ea7\u54c1\u6982\u89c8<\/h2>\n<p>The IS61LV25616AL-10TL is a 4Mbit (256K x 16-bit) high-speed low-power asynchronous SRAM from ISSI operating at 3.3V with 10 ns access time. It features upper\/lower byte control (LB#, UB#) and is packaged in a 44-pin TSOP II, making it ideal for high-performance cache and buffer applications.<\/p>\n<h2>\u4e3b\u8981\u89c4\u683c<\/h2>\n<table>\n<tr>\n<td>Density<\/td>\n<td>4Mbit (256K x 16)<\/td>\n<\/tr>\n<tr>\n<td>\u7535\u6e90\u7535\u538b<\/td>\n<td>3.3V (2.7V to 3.6V)<\/td>\n<\/tr>\n<tr>\n<td>Access Time<\/td>\n<td>10 ns<\/td>\n<\/tr>\n<tr>\n<td>Interface<\/td>\n<td>Parallel asynchronous<\/td>\n<\/tr>\n<tr>\n<td>Byte Control<\/td>\n<td>LB#, UB#<\/td>\n<\/tr>\n<tr>\n<td>Operating Current<\/td>\n<td>~80 mA<\/td>\n<\/tr>\n<tr>\n<td>Operating Temp<\/td>\n<td>-40\u00b0C to +85\u00b0C<\/td>\n<\/tr>\n<tr>\n<td>\u5305\u88c5<\/td>\n<td>44-pin TSOP II<\/td>\n<\/tr>\n<tr>\n<td>\u90e8\u4ef6\u72b6\u6001<\/td>\n<td>\u6d3b\u8dc3<\/td>\n<\/tr>\n<\/table>\n<h2>\u7279\u70b9<\/h2>\n<ul>\n<li>4Mbit (256K x 16) high-speed SRAM<\/li>\n<li>10 ns access time \u2014 fastest in class<\/li>\n<li>3.3V low-power operation<\/li>\n<li>Upper\/lower byte control (LB#, UB#)<\/li>\n<li>Fully static, no refresh or clocks<\/li>\n<li>Industrial temperature range<\/li>\n<\/ul>\n<h2>\u5e94\u7528<\/h2>\n<ul>\n<li>High-speed cache memory<\/li>\n<li>Networking and telecom buffer<\/li>\n<li>Graphics and video frame buffer<\/li>\n<li>DSP and FPGA external SRAM<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The IS61LV25616AL-10TL is a 4Mbit (256K x 16-bit) high-speed low-power asynchronous SRAM from ISSI operating at 3.3V with 10 ns access time. It features upper\/lower byte control (LB#, UB#) and is packaged in a 44-pin TSOP II, making it ideal for high-performance cache and buffer applications. Key Specifications Density 4Mbit (256K x 16) [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[3327],"chip_brand":[210],"class_list":["post-12333","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","tag-is61lv25616al-10tl","chip_brand-issi"],"acf":{"brief_explanation":"4Mb (256Kx16) high-speed SRAM, 3.3V, 10ns, byte ctrl, 44-TSOP II","date_code":"","package_case":"44-pin TSOP II","in_stock":7654,"datasheet":"https:\/\/www.issi.com\/WW\/pdf\/61LV25616AL.pdf","price":"$6.50 @ 1pc","product_introduction":"The IS61LV25616AL-10TL is a 4Mbit (256K x 16-bit) high-speed low-power asynchronous SRAM from ISSI operating at 3.3V with 10 ns access time. The fast 10ns access makes it ideal for cache and high-performance buffer applications. Upper\/lower byte control via LB# and UB# enables flexible 8-bit or 16-bit bus access. The 44-pin TSOP II package is widely supported in embedded and networking designs.","working_principle":"Fully static asynchronous SRAM with 10ns access time. Read: CE# low, OE# low \u2014 data appears on DQ after 10ns. Write: CE# low, WE# low with byte select via LB#\/UB#. The 10ns speed supports 100 MHz bus operation, suitable for high-performance cache and networking buffer applications.","pin_description":"<table><tr><th>Pin Group<\/th><th>Interface<\/th><th>Function<\/th><\/tr><tr><td>A0-A17<\/td><td>Input<\/td><td>18-bit address inputs<\/td><\/tr><tr><td>DQ0-DQ7<\/td><td>I\/O<\/td><td>Lower byte data<\/td><\/tr><tr><td>DQ8-DQ15<\/td><td>I\/O<\/td><td>Upper byte data<\/td><\/tr><tr><td>CE#, OE#, WE#<\/td><td>Input<\/td><td>Control signals<\/td><\/tr><tr><td>LB#, UB#<\/td><td>Input<\/td><td>Byte enable<\/td><\/tr><\/table>","application_scenarios":"<ul><li>FPGA\/CPU L2 cache memory<\/li><li>Networking packet buffer at 100MHz<\/li><li>High-speed DSP external SRAM<\/li><\/ul>","alternative_models":"<table><tr><th>Manufacturer<\/th><th>Part Number<\/th><th>Package<\/th><th>Notes<\/th><\/tr><tr><td>ISSI<\/td><td>IS61WV51216EDBLL-10TLI<\/td><td>TSOP<\/td><td>8Mbit 10ns upgrade<\/td><\/tr><tr><td>Cypress<\/td><td>CY7C1041CV33-10ZSXI<\/td><td>TSOP<\/td><td>4Mbit 10ns alternative<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts\/12333","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/comments?post=12333"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts\/12333\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/media?parent=12333"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/categories?post=12333"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/tags?post=12333"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=12333"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}