The CSD87350Q5D from Texas Instruments is a 30-V, 40-A synchronous buck NexFET power block in an 8-pin LSON (5\u00d76 mm) package. It integrates an asymmetrical dual N-channel MOSFET pair (control FET + sync FET) optimized for 5-V gate drive synchronous buck converters. Key specs include 5.9-m\u03a9 RDS(on) max at 20 A \/ 8 V for the control FET, 90% system efficiency at 25 A (12-V input, 1.3-V output, 500 kHz), switching frequency up to 1.5 MHz, and 12-W power dissipation. The ultra-low inductance package minimizes parasitic ringing. Targeted at server VRM, IMVP, POL DC-DC, and multiphase buck converters operating from 5-V to 27-V input rails.<\/p>","protected":false},"excerpt":{"rendered":"
The CSD87350Q5D from Texas Instruments is a 30-V, 40-A synchronous buck NexFET power block in an 8-pin LSON (5\u00d76 mm) package. It integrates an asymmetrical dual N-channel MOSFET pair (control FET + sync FET) optimized for 5-V gate drive synchronous buck converters. Key specs include 5.9-m\u03a9 RDS(on) max at 20 A \/ 8 V for […]<\/p>\n","protected":false},"author":2,"featured_media":2873,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,55],"tags":[],"chip_brand":[138],"class_list":["post-2040","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-transistors","chip_brand-ti"],"acf":{"brief_explanation":"30V 40A NexFET power block, 5.9m\u03a9, 90% eff@25A, 5V gate drive, LSON-8 5x6mm, up to 1.5MHz, -55~150\u00b0C","date_code":"","package_case":"LSON-CLIP-8 (5.0 x 6.0 x 1.0 mm, land pattern per datasheet)","in_stock":5400,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/csd87350q5d.pdf","price":"$1.25 (1K+ pcs)","product_introduction":"The CSD87350Q5D is a NexFET power block from Texas Instruments that integrates a half-bridge MOSFET pair (control FET and sync FET) in a single 5\u00d76-mm LSON package. It is specifically optimized for 5-V gate drive synchronous buck converters used in server VRM, IMVP, and high-current POL applications.\n\nThe power block approach integrates both MOSFETs and their interconnection in one package, dramatically reducing parasitic inductance between the control and sync FETs. This ultra-low inductance (sub-100 pH) minimizes switch-node ringing and overshoot, allowing higher switching frequencies without excessive voltage stress on the devices. The result is higher efficiency and smaller output filter components.\n\nThe control FET (Q1) is optimized for low switching losses with low gate charge (8.4 nC typical at 4.5 V), while the sync FET (Q2) is optimized for low conduction losses with very low RDS(on). This asymmetrical design is the key to achieving 90% system efficiency at 25 A output (12 V to 1.3 V at 500 kHz), with only 3 W total power loss.\n\nThe LSON-CLIP-8 package uses a copper clip internal interconnect instead of wire bonds, providing the lowest possible parasitic inductance and resistance. The exposed thermal pad (PGND) achieves 2\u00b0C\/W junction-to-case thermal resistance, enabling efficient heat removal through the PCB ground plane.\n\nThe device is rated for 40-A continuous operation and 120-A pulsed current, making it suitable for high-current single-phase and multiphase buck converters. The 30-V drain-to-source voltage covers 12-V, 19-V, and 24-V input rails. Switching frequency support up to 1.5 MHz allows very small inductors in space-constrained designs.\n\nThe CSD87350Q5D is designed to pair with TI's TPS53819A and similar multi-phase controllers for server CPU\/GPU VRM applications, but can be driven by any 5-V gate driver for standalone POL converters.","working_principle":"**Half-Bridge Configuration:** The CSD87350Q5D integrates two N-channel MOSFETs in a half-bridge: Q1 (control FET, high-side) and Q2 (sync FET, low-side). The switch node (SW) connects between Q1 source and Q2 drain. Q1 connects from VIN to SW, Q2 from SW to PGND. During Q1 on-time, inductor current flows from VIN through Q1 to the output. During Q2 on-time, inductor current freewheels through Q2 from PGND to SW.\n\n**Asymmetrical MOSFET Optimization:** Q1 (control FET) is optimized for fast switching with low gate charge (Qg = 8.4 nC) and moderate RDS(on). Q2 (sync FET) is optimized for low conduction loss with very low RDS(on) since it conducts for a larger fraction of the switching cycle at low duty cycles. This asymmetry is fundamental to efficient buck converter design.\n\n**Copper Clip Interconnect:** Traditional discrete MOSFET solutions use wire bonds between the control FET drain and sync FET drain, adding 0.5-2 nH of parasitic inductance. The CSD87350Q5D uses a copper clip that directly connects the two FETs internally, reducing loop inductance to sub-100 pH. This dramatically reduces switch-node ringing, allowing higher dv\/dt transitions without exceeding voltage ratings.\n\n**Gate Drive Interface:** The TG (top gate) and BG (bottom gate) pins connect directly to an external gate driver IC. The TGR (top gate return) pin is the high-side return path (connected to SW). The 5-V gate drive optimization means the FETs are designed for RDS(on) specified at VGS = 4.5-8 V, with threshold voltages of 1.0 V (Q1) and 0.75 V (Q2) for logic-level compatibility.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | VSW<\/td> | O<\/td> | Switch node; Q1 source \/ Q2 drain; connect to output inductor; high dv\/dt switching node; keep copper area minimal to reduce EMI<\/td><\/tr> | ||||||||||||||||||||||||||||
| 2<\/td> | VSW<\/td> | O<\/td> | Switch node (parallel with pin 1); doubled for current capacity and thermal distribution<\/td><\/tr> | ||||||||||||||||||||||||||||
| 3<\/td> | VSW<\/td> | O<\/td> | Switch node (parallel with pins 1,2)<\/td><\/tr> | ||||||||||||||||||||||||||||
| 4<\/td> | BG<\/td> | I<\/td> | Bottom gate drive input; drives Q2 (sync FET) gate; connect to gate driver low-side output; referenced to PGND<\/td><\/tr> | ||||||||||||||||||||||||||||
| 5<\/td> | TGR<\/td> | I<\/td> | Top gate return; high-side gate drive return path; connects to switch node (VSW); bootstrap capacitor return<\/td><\/tr> | ||||||||||||||||||||||||||||
| 6<\/td> | TG<\/td> | I<\/td> | Top gate drive input; drives Q1 (control FET) gate; connect to gate driver high-side output; referenced to TGR (SW)<\/td><\/tr> | ||||||||||||||||||||||||||||
| 7<\/td> | PGND<\/td> | G<\/td> | Power ground; Q2 source and thermal pad; connect to PCB ground plane with maximum copper; critical for thermal performance (R\u03b8JC = 2\u00b0C\/W)<\/td><\/tr> | ||||||||||||||||||||||||||||
| 8<\/td> | VIN<\/td> | P<\/td> | Input supply; Q1 drain; connect to input bypass capacitors (6x 10\u00b5F ceramic recommended); two VIN pins for current distribution<\/td><\/tr> | ||||||||||||||||||||||||||||
| Pad<\/td> | PGND\/Thermal<\/td> | G<\/td> | Exposed thermal pad; electrically connected to PGND; must be soldered to PCB ground plane with thermal vias for heat removal<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|