The AT24C04C-SSHM-B from Microchip Technology is a 4 Kbit (512 x 8) I2C serial EEPROM in an 8-pin SOIC package. It operates from 1.7 V to 5.5 V with 400 kHz (1.7 V) and 1 MHz (>2.5 V) clock compatibility. Key features include 16-byte page write, 5 ms maximum write cycle time, 1 million erase\/write cycle endurance, 100-year data retention, and hardware write-protect pin (WP). The device supports up to 4 devices on the same I2C bus via A0\/A1\/A2 address pins. The SSHM-B suffix denotes SOIC-8 tube packaging, -40\u00b0C to +85\u00b0C industrial temperature range.<\/p>","protected":false},"excerpt":{"rendered":"
The AT24C04C-SSHM-B from Microchip Technology is a 4 Kbit (512 x 8) I2C serial EEPROM in an 8-pin SOIC package. It operates from 1.7 V to 5.5 V with 400 kHz (1.7 V) and 1 MHz (>2.5 V) clock compatibility. Key features include 16-byte page write, 5 ms maximum write cycle time, 1 million erase\/write […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[40,13],"tags":[],"chip_brand":[134],"class_list":["post-2062","post","type-post","status-publish","format-standard","hentry","category-electrically-erasable-programmable-read-only-memory-eeprom","category-integrated-circuits-ics","chip_brand-microchip"],"acf":{"brief_explanation":"4Kbit I2C EEPROM, 512x8, 1MHz@2.5V, 1M cycles, 100yr retention, WP pin, SOIC-8, -40~85\u00b0C","date_code":"","package_case":"SOIC-8 (4.9 x 3.9 x 1.5 mm, 1.27mm pitch)","in_stock":10490,"datasheet":"https:\/\/ww1.microchip.com\/downloads\/en\/DeviceDoc\/AT24C04C-08C-I2C-Compat-2-Wire-Serial-EEPROM-4Kb-8Kb-DS20006127.pdf","price":"$0.28 (1+ pcs)","product_introduction":"The AT24C04C from Microchip (originally Atmel) is a 4 Kbit I2C serial EEPROM organized as 512 x 8 bits. The AT24C04C-SSHM-B is the SOIC-8 tube-packaged version for the -40\u00b0C to +85\u00b0C industrial temperature range. It is part of the AT24CxxC family, which also includes the AT24C01C (1 Kbit), AT24C02C (2 Kbit), and AT24C08C (8 Kbit) with identical pinouts and protocols.\n\nThe device supports two I2C speed modes: Standard-mode (400 kHz) at 1.7 V and Fast-mode Plus (1 MHz) at 2.5 V and above. The 16-byte page write buffer allows writing up to 16 bytes in a single I2C transaction, after which the internal write cycle completes in 5 ms maximum. Random and sequential read modes support single-byte and continuous read operations.\n\nThe hardware write-protect pin (WP) protects the entire memory array when pulled HIGH, preventing accidental or malicious writes. This is useful for calibration data, serial numbers, and configuration parameters that must not change in the field.\n\nThree address pins (A0, A1, A2) allow up to four AT24C04C devices to share the same I2C bus, providing a total of 16 Kbit of EEPROM on a single bus. The device uses the standard Atmel I2C EEPROM protocol with a 7-bit slave address (1010 + A2A1A0 + R\/W).\n\nThe 1.7 V minimum supply voltage enables direct operation from single-cell Li-ion batteries (2.7-4.2 V) and 1.8 V logic systems. The 6 \u00b5A maximum standby current preserves battery life in always-connected applications.\n\nAn automotive-qualified version (AT24C04C-STPD-TVAO, AEC-Q100 Grade 1, -40\u00b0C to +125\u00b0C) is available for automotive applications.","working_principle":"**I2C Interface Protocol:** The AT24C04C communicates via the standard I2C protocol. The master initiates communication with a START condition, followed by the 7-bit device address (1010 + A2A1A0) and a R\/W bit. The EEPROM acknowledges (ACK) by pulling SDA low on the 9th clock. Data is transferred MSB first, 8 bits per byte, with ACK after each byte.\n\n**Write Operation:** For byte write, the master sends device address + write, then the 8-bit word address, then data byte, then STOP. The EEPROM enters an internal write cycle (5 ms max) during which it does not respond to I2C commands. Page write works similarly but accepts up to 16 data bytes; the lower 4 address bits auto-increment and wrap within the page.\n\n**Read Operation:** Random read requires a dummy write sequence (device address + write, word address, RESTART, device address + read) to set the address counter, then data is clocked out. Current address read starts from the last accessed address + 1. Sequential read continues indefinitely until the master sends NACK + STOP.\n\n**Memory Cell Technology:** The EEPROM uses floating-gate MOS transistors. Write operations inject charge onto the floating gate via Fowler-Nordheim tunneling through a thin oxide layer. Erase removes the charge. The high-quality oxide provides 100-year data retention and 1 million cycle endurance.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | A0<\/td> | I<\/td> | Address input bit 0; sets slave address bit; connect to VCC or GND; must be defined for proper bus operation; pin also used for chip selection on multi-device bus<\/td><\/tr> | ||||||||||||||||||||||||||||
| 2<\/td> | A1<\/td> | I<\/td> | Address input bit 1; same as A0; for AT24C04C, only A2 and A1 are used for address (up to 4 devices); A0 is don't care<\/td><\/tr> | ||||||||||||||||||||||||||||
| 3<\/td> | A2<\/td> | I<\/td> | Address input bit 2; most significant address bit; must connect to VCC or GND; do not leave floating<\/td><\/tr> | ||||||||||||||||||||||||||||
| 4<\/td> | GND<\/td> | G<\/td> | Ground; connect to PCB ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||
| 5<\/td> | SDA<\/td> | I\/O<\/td> | Serial data; open-drain I2C data line; requires external pull-up resistor (typically 4.7k\u03a9); bidirectional<\/td><\/tr> | ||||||||||||||||||||||||||||
| 6<\/td> | SCL<\/td> | I<\/td> | Serial clock; I2C clock from master; up to 400kHz at 1.7V or 1MHz at >2.5V; requires pull-up if master has open-drain output<\/td><\/tr> | ||||||||||||||||||||||||||||
| 7<\/td> | WP<\/td> | I<\/td> | Write protect; active HIGH; when HIGH, the entire memory array is write-protected; when LOW or NC, normal read\/write operation; connect to GND for normal operation<\/td><\/tr> | ||||||||||||||||||||||||||||
| 8<\/td> | VCC<\/td> | P<\/td> | Supply voltage; 1.7V to 5.5V; bypass with 0.1\u00b5F ceramic to GND; 6\u00b5A max standby current<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
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