{"id":7579,"date":"2026-06-26T04:46:31","date_gmt":"2026-06-26T04:46:31","guid":{"rendered":"https:\/\/ic-vendor.com\/cd4021be\/"},"modified":"2026-06-26T04:46:31","modified_gmt":"2026-06-26T04:46:31","slug":"cd4021be","status":"publish","type":"post","link":"https:\/\/ic-vendor.com\/zh\/cd4021be\/","title":{"rendered":"CD4021BE"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The CD4021BE is a CMOS 8-stage static shift register with asynchronous parallel load, 3V-18V supply, and 8.5MHz max clock in 16-pin DIP through-hole package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\u914d\u7f6e<\/td>\n8-bit universal shift register<\/td>\n<\/tr>\n
Technology<\/td>\nCD4000 CMOS<\/td>\n<\/tr>\n
Number of Bits<\/td>\n8<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n3 V to 18 V<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n8.5 MHz @ 10V<\/td>\n<\/tr>\n
Output Drive Current<\/td>\n4.2 mA sink\/source @ 5V<\/td>\n<\/tr>\n
Supply Current (max)<\/td>\n3 mA @ 15V<\/td>\n<\/tr>\n
\u8f93\u5165\u7c7b\u578b<\/td>\n\u6807\u51c6 CMOS<\/td>\n<\/tr>\n
\u8f93\u51fa\u7c7b\u578b<\/td>\nPush-Pull<\/td>\n<\/tr>\n
Parallel Load<\/td>\nAsynchronous (active high PE)<\/td>\n<\/tr>\n
Serial Output<\/td>\nQ6, Q7, Q8 available<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\n16-pin PDIP (BE suffix)<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n-55 to +125 C<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • 8-stage static shift register with parallel load capability<\/li>\n
  • Asynchronous parallel load overrides serial shift<\/li>\n
  • 3V to 18V wide supply voltage range<\/li>\n
  • Three serial outputs: Q6, Q7, Q8 for cascading flexibility<\/li>\n
  • CD4000 CMOS family for industrial robustness<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Parallel-to-serial data conversion<\/li>\n
    • Input expansion for microcontroller systems<\/li>\n
    • Key scanning and switch matrix reading<\/li>\n
    • Delayed data output using multiple tap points<\/li>\n
    • General-purpose logic and shift register functions<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CD4021BE is a CMOS 8-stage static shift register with asynchronous parallel load, 3V-18V supply, and 8.5MHz max clock in 16-pin DIP through-hole package. Key Specifications Configuration 8-bit universal shift register Technology CD4000 CMOS Number of Bits 8 Supply Voltage 3 V to 18 V Max Clock Frequency 8.5 MHz @ 10V Output […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,22],"tags":[],"chip_brand":[138],"class_list":["post-7579","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-video-ics","chip_brand-ti"],"acf":{"brief_explanation":"8-bit CMOS shift register, parallel load, 3-18V, PDIP-16","date_code":"","package_case":"16-pin PDIP (19.3 x 6.35 x 5.08 mm, through-hole)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4021b.pdf","price":"$0.65 @ 1ku","product_introduction":"The CD4021BE is a CMOS 8-stage static shift register with asynchronous parallel load in 16-pin PDIP package. The device operates from 3V to 18V supply and features both serial-in\/serial-out shift capability and 8-bit parallel load via the parallel enable (PE) input. When PE is high, the 8 parallel inputs (P1-P8) are asynchronously loaded into the register, overriding the serial shift data. When PE is low, data shifts from the serial input (SI) through the 8 stages on each rising clock edge. Three serial outputs (Q6, Q7, Q8) provide access to different tap points for cascading flexibility. The BE suffix denotes 16-pin plastic DIP package with extended temperature range.","working_principle":"The CD4021BE operates as an 8-bit static shift register with parallel load. (1) In serial shift mode (PE = low), data present at the serial input (SI) is shifted into the first stage on each rising clock edge. The data in each stage shifts one position to the right, and the Q8 output reflects the data shifted out of the last stage. This mode is used for serial-in\/serial-out and serial-in\/parallel-out data transfer. The Q6 and Q7 outputs provide intermediate tap points for applications requiring shorter delay or cascading at intermediate positions. (2) In parallel load mode (PE = high), the 8 parallel inputs (P1-P8) are asynchronously loaded into the register regardless of the clock state. This overrides any serial data and immediately updates all 8 register stages. This mode is essential for parallel-to-serial conversion: first load 8 bits in parallel, then shift them out serially at Q8. (3) The asynchronous nature of the parallel load means it takes priority over the clock. When PE goes high, the parallel data is loaded immediately without waiting for a clock edge. When PE returns low, the device resumes serial shifting from the loaded state. This makes the CD4021BE ideal for reading parallel data (such as switch matrices or keyboard inputs) and converting it to serial for transmission to a microcontroller via a single data line.","pin_description":"
      Pin<\/th>Name<\/th>Function<\/th><\/tr>
      1<\/td>P6<\/td>Parallel input 6<\/td><\/tr>
      2<\/td>P7<\/td>Parallel input 7<\/td><\/tr>
      3<\/td>P8<\/td>Parallel input 8<\/td><\/tr>
      4<\/td>Q6<\/td>Serial output (stage 6)<\/td><\/tr>
      5<\/td>Q7<\/td>Serial output (stage 7)<\/td><\/tr>
      6<\/td>Q8<\/td>Serial output (stage 8)<\/td><\/tr>
      7<\/td>CLK<\/td>Clock (rising edge shifts)<\/td><\/tr>
      8<\/td>VSS<\/td>Ground<\/td><\/tr>
      9<\/td>SI<\/td>Serial data input<\/td><\/tr>
      10<\/td>PE<\/td>Parallel Enable (active high)<\/td><\/tr>
      11<\/td>P1<\/td>Parallel input 1<\/td><\/tr>
      12<\/td>P2<\/td>Parallel input 2<\/td><\/tr>
      13<\/td>P3<\/td>Parallel input 3<\/td><\/tr>
      14<\/td>P4<\/td>Parallel input 4<\/td><\/tr>
      15<\/td>P5<\/td>Parallel input 5<\/td><\/tr>
      16<\/td>VDD<\/td>Positive supply (3-18V)<\/td><\/tr><\/table>","application_scenarios":"
      • Parallel-to-serial data conversion for MCU input expansion<\/li>
      • Key scanning and switch matrix reading via parallel load<\/li>
      • Delayed data output using Q6\/Q7\/Q8 tap points<\/li>
      • General-purpose logic and shift register functions at 3-18V<\/li>
      • Industrial control systems requiring wide voltage range<\/li><\/ul>","alternative_models":"
        Model<\/th>Manufacturer<\/th>Key Difference<\/th><\/tr>
        CD4014BE<\/td>TI<\/td>Synchronous parallel load (vs async)<\/td><\/tr>
        74HC165D<\/td>Nexperia<\/td>8-bit, 2-6V, async load, SO-16<\/td><\/tr>
        74HC589D<\/td>Nexperia<\/td>8-bit, output latch, SO-16<\/td><\/tr>
        CD4094BE<\/td>TI<\/td>8-bit serial-in\/parallel-out<\/td><\/tr>
        74LV165APW<\/td>Nexperia<\/td>8-bit, 1.2-5.5V, TSSOP-16<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts\/7579","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/comments?post=7579"}],"version-history":[{"count":0,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/posts\/7579\/revisions"}],"wp:attachment":[{"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/media?parent=7579"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/categories?post=7579"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/tags?post=7579"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/ic-vendor.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7579"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}