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GTL2014PWZ

4-bit GTL-to-LVTTL translator, >200MHz, TSSOP-20

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GTL2014PWZ

Paquete：

TSSOP-20

Marca：
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Descripción

Productos

The GTL2014PWZ from NXP is a 4-bit GTL (Gunning Transceiver Logic) to LVTTL level translator with >200 MHz bandwidth. It converts GTL backplane signals (typically 0.6V-1.5V) to 3.3V LVTTL levels for processor or FPGA interface.

Especificaciones

Función 4-bit GTL-to-TTL level translator
Canales 4 (unidirectional GTL to LVTTL)
GTL Reference External Vref (0.6-1.5V)
LVTTL Supply 3.3V
Bandwidth >200 MHz
Paquete TSSOP-20 (6.5×4.4mm)

Principio de funcionamiento

Four unidirectional channels translate GTL open-drain signals (referenced to an external VREF, typically 0.8V) to LVTTL levels. GTL receivers compare incoming signals against VREF and drive CMOS outputs at 3.3V LVTTL levels. This enables direct connection between GTL backplanes and LVTTL logic without external resistors.

Aplicaciones

  • GTL backplane to LVTTL interface
  • Server / workstation bus bridging
  • Memory controller interface

The GTL2014PWZ from NXP is a 4-bit GTL (Gunning Transceiver Logic) to LVTTL level translator with >200 MHz bandwidth. It converts GTL backplane signals (typically 0.6V-1.5V) to 3.3V LVTTL levels for processor or FPGA interface.

Four unidirectional channels translate GTL open-drain signals (referenced to an external VREF, typically 0.8V) to LVTTL levels. GTL receivers compare incoming signals against VREF and drive CMOS outputs at 3.3V LVTTL levels. This enables direct connection between GTL backplanes and LVTTL logic without external resistors.

Pin Nombre Descripción
1 VREF GTL reference voltage
2-5 GTL0-3 GTL inputs
6 GND Suelo
7-10 TTL0-3 LVTTL outputs
11 VCC 3.3V supply
  • GTL backplane to LVTTL interface
  • Server / workstation bus bridging
  • Memory controller interface
Modelo Fabricante Diferencia clave
GTL2004 NXP Similar GTL translator
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