LM5069MM-1

The LM5069MM-1 is a high-voltage hot swap controller from Texas Instruments, designed to enable safe insertion and removal of printed circuit boards from live backplane systems. Operating from 9V to 80V, this device is well-suited for 24V industrial systems, 48V telecom infrastructure, and high-voltage server power architectures.

Hot swap controllers prevent damage to connectors, components, and the backplane by controlling the inrush current when a board is plugged into a live power bus. The LM5069 achieves this by slowly ramping the gate of an external N-channel MOSFET, allowing the output voltage and load current to rise in a controlled manner. This eliminates the large capacitive charging currents that would otherwise flow into the board’s bulk capacitors.

The LM5069 features both current limiting and power limiting for comprehensive MOSFET protection. The current limit is set by an external sense resistor (50mV threshold), while the power limit is programmed by a resistor on the TIMER pin. Power limiting ensures the MOSFET operates within its safe operating area (SOA) even during fault conditions.

Version -1 of the LM5069 features a latch-off fault response: when an overcurrent fault persists beyond the programmed fault time, the GATE pin is pulled low and the device latches off. The device remains off until power is recycled or the UVLO/EN pin is toggled. The VSSOP-10 package provides a compact solution for space-constrained designs.

The LM5069 operates as a hot swap controller with the following functional blocks:

1. Undervoltage Lockout (UVLO): The UVLO/EN pin must rise above its 1.25V threshold for the device to start up. An external resistor divider from VIN to GND sets the UVLO threshold. Below this threshold, the GATE pin is held low and the MOSFET is off.

2. Power-Up and Inrush Control: When UVLO is satisfied, the charge pump begins powering the GATE pin through an internal current source. The GATE voltage rises, and as the MOSFET begins to conduct, the output voltage (V_OUT) ramps up. The inrush current is controlled by the rate of V_OUT rise and the value of the output capacitance. The TIMER capacitor sets the soft-start / power-up timeout.

3. Current Limiting: During normal operation, the device monitors the voltage across the external sense resistor (R_SNS) between VIN and SNS pins. If the load current exceeds the programmed limit (I_LIMIT = 50mV / R_SNS), the gate drive is reduced to regulate the current at the limit level. The fault timer starts charging.

4. Power Limiting: In addition to current limiting, the LM5069 measures the voltage across the MOSFET (V_IN – V_OUT) and the load current, then limits the power dissipation (P = V × I) of the external MOSFET. This ensures the MOSFET operates within its SOA boundaries, especially during start-up into heavy capacitive loads or fault conditions.

5. Fault Response (Latch-off, Version -1): If the overcurrent or power-limiting condition persists beyond the programmed fault timeout (set by TIMER capacitor), the GATE pin is pulled low, turning off the MOSFET. The device latches in the off state. To reset, either cycle VIN below UVLO or toggle the UVLO/EN pin.

6. Power Good Output: The PGD pin is an open-drain output that goes low when V_OUT rises above approximately 92% of VIN (the MOSFET is fully on), indicating that power is good.

• 48V telecom line card and server blade hot swap
• 24V industrial PLC module plug-in protection
• Redundant power supply OR-ing and load sharing
• Electronic circuit breaker / eFuse for high-voltage buses
• Battery management and load switching systems