AD5024BRUZ

The AD5024BRUZ is a high-precision, quad-channel 12-bit digital-to-analog converter from Analog Devices’ nanoDAC® product family. Designed for applications requiring high accuracy and low power in a compact form factor, this device offers ±1 LSB integral nonlinearity (INL) and ±1 LSB differential nonlinearity (DNL) specifications, delivering fully accurate 12-bit performance across all four channels. Each channel features an integrated output buffer amplifier with rail-to-rail operation, eliminating the need for external operational amplifiers. The AD5024 operates from a single 4.5V to 5.5V supply and includes internal reference buffers for all reference pins. The device provides individual reference voltage pins for each DAC pair (VREFA for DAC A, VREFB for DAC B, etc.), giving designers flexibility to use different reference voltages on different channels. The versatile 3-wire serial interface operates at clock speeds up to 50 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards, enabling easy integration into a wide range of digital systems. An SDO output pin supports daisy-chaining multiple DACs on a single serial bus for systems requiring many output channels. Comprehensive control features include a hardware LDAC (Load DAC) pin that can be used to simultaneously update all DAC outputs, with a software LDAC override function for per-channel update control. An asynchronous CLR input clears all DAC outputs to a programmable code. The AD5024 incorporates a power-on reset circuit that ensures all DAC outputs power up to a known state (either zero scale or midscale, selected via the POR pin), preventing glitches or unexpected outputs during power-up. Three software-selectable power-down modes allow each channel to be independently placed in a low-power state with output pulled to ground through a 1kΩ or 100kΩ resistor, or set to high-impedance. In power-down mode, the typical supply current drops to just 400 nA at 5V, making the device well-suited for battery-powered applications. Total unadjusted error (TUE) is specified at less than 2 mV, ensuring excellent DC accuracy. The AD5024BRUZ is packaged in a space-saving 16-lead TSSOP package and is fully specified over the industrial temperature range of -40°C to +125°C. As part of the pin-compatible AD5024/AD5044/AD5064 family (12/14/16-bit respectively), the AD5024BRUZ provides an upgrade path for existing AD5666 designs.

The AD5024BRUZ is a four-channel 12-bit digital-to-analog converter based on a resistor string (R-string) DAC architecture with integrated output buffer amplifiers. Each DAC channel consists of a 12-bit input register, a DAC register, and an R-string DAC followed by a rail-to-rail output buffer amplifier. The R-string architecture provides inherent monotonicity (the output always increases with increasing digital code) and very low glitch energy, which is important for applications where code transition glitches could cause problems. The digital input data is loaded through the 3-wire SPI-compatible serial interface. Each 32-bit write sequence includes 8 command bits, 4 address bits, and 12 data bits (for the 12-bit AD5024), along with additional don’t care bits for the lower resolutions. The command bits determine the operation (write to input register, update DAC register, write and update, power-down, etc.), and the address bits select which DAC channel or channels are affected. The double-buffered architecture (input register and DAC register) allows new data to be preloaded into the input registers while the DAC outputs maintain their current values. When the LDAC signal is asserted (either via hardware pin or software command), all DAC registers are simultaneously updated from their respective input registers, providing synchronized output updates across all channels. Alternatively, each channel can be updated individually by writing directly to both registers in a single write operation. The reference voltage is applied to dedicated VREF pins, with internal reference buffers ensuring high input impedance and isolating the reference from internal switching transients. The output buffer amplifiers provide rail-to-rail output swing, meaning the output voltage can approach both ground and the reference voltage, maximizing the usable output range. Power-on reset circuitry ensures all DAC registers and outputs initialize to a known state (zero scale or midscale) when power is first applied, preventing unexpected output voltages during system startup. The power-down feature reduces supply current to nanoamp levels by turning off the output buffer and placing the output in a high-impedance state or connecting it to ground through a resistor. The CLR function asynchronously clears all DAC outputs to a user-programmable value stored in the clear code register, providing a quick reset to a predefined level.

• Process control loop output and setpoint generation
• Data acquisition systems and automatic test equipment (ATE)
• Portable battery-powered instruments and measurement devices
• Digital gain, offset, and bias voltage adjustment in signal chains
• Programmable voltage and current source designs
• Programmable attenuators and variable gain amplifier control
• Sensor calibration and precision trimming applications
• Motor control bias generation and reference programming
• Optical transceiver module bias control and calibration
• Automotive sensor and actuator control circuits
• Industrial PLC analog output modules