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SN74LVC2G04DCKR

Dual inverter gate, 1.65-5.5V, +-24mA drive, 4.1ns tpd, SC-70-6

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Pieza del fabricante：

SN74LVC2G04DCKR

Paquete：

SC-70-6 (2.0 x 1.25 x 0.95 mm)

Marca：
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Descripción

Productos

The SN74LVC2G04DCKR from Texas Instruments is a dual inverter gate designed for 1.65-V to 5.5-V VCC operation in a 6-pin SC-70 (DCK) package. It performs the Boolean function Y = NOT(A) and features +-24-mA output drive at 3.3 V, making it suitable for high-speed logic inversion in space-constrained applications.

Especificaciones

Número de canales 2
Supply Voltage Range 1.65 V to 5.5 V
Output Drive +-24 mA at 3.3 V
Max Propagation Delay 4.1 ns at 3.3 V
Supply Current 10 uA (max)
Temperatura de funcionamiento -40 to 125 degC
Paquete SC-70-6 (2.0 x 1.25 mm)

Características

  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Low power consumption: 10-uA max ICC
  • Ioff supports partial-power-down mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Available in NanoFree package technology

Aplicaciones

  • Logic level inversion and signal conditioning
  • Clock signal inversion
  • Bus interface logic
  • Portable electronics
  • Mixed-voltage system translation

The SN74LVC2G04DCKR is a dual inverter gate from Texas Instruments designed for 1.65-V to 5.5-V VCC operation. Each inverter performs the Boolean function Y = NOT(A). The device features high output drive capability of +-24 mA at 3.3 V with a maximum propagation delay of 4.1 ns, making it ideal for high-speed logic inversion in compact designs. The SC-70-6 (DCK) package occupies minimal board space, and the Ioff circuitry supports partial-power-down mode operation by disabling outputs when VCC is zero.

The SN74LVC2G04DCKR contains two independent CMOS inverter gates. Each gate uses a complementary PMOS-NMOS push-pull output stage that actively drives the output high or low. When the input is at logic low, the PMOS transistor turns on pulling the output high; when the input is at logic high, the NMOS transistor turns on pulling the output low. The Ioff circuit uses isolation transistors that disconnect the output when VCC is zero, preventing parasitic conduction paths. The input protection structure allows voltages up to 5.5 V regardless of VCC, enabling mixed-voltage interfacing.

Pin Nombre Tipo Función
1 1A Entrada Inverter 1 input
2 1Y Salida Inverter 1 output
3 GND Potencia Suelo
4 2Y Salida Inverter 2 output
5 2A Entrada Inverter 2 input
6 VCC Potencia Supply voltage
  • Logic signal inversion in compact designs
  • Clock and data signal conditioning
  • Mixed-voltage logic level translation
  • Portable battery-powered electronics
  • Active-low to active-high signal conversion
Fabricante Número de pieza Paquete Notas
TI SN74LVC1G04DCKR SC-70-5 Single inverter version
Nexperia 74LVC2G04DP TSSOP-8 Dual inverter, TSSOP
TI SN74LVC2G14DCKR SC-70-6 Dual Schmitt-trigger inverter
Nexperia 74LVC2G04GV SOT-363 Pin-compatible equivalent
onsemi NC7SZ04P5X SOT-23-5 Single inverter, similar spec
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