TPS54620RHLR

The TPS54620RHLR from Texas Instruments is a 6A synchronous step-down DC/DC converter from the SWIFT (Switcher With Integrated FET Technology) family, featuring a 4.5V to 17V input range and an adjustable output from 0.8V to 5.5V. The device integrates a 26mOhm high-side MOSFET and a 19mOhm low-side MOSFET in a compact 3.5×3.5mm VQFN-14 package, delivering high efficiency in a small footprint. The separate PVIN rail allows the power stage to operate from a different voltage (1.6V to 17V) than the control circuitry, enabling flexible power architecture designs. The current-mode control with external compensation provides design flexibility across a wide range of output inductors and capacitors. The switching frequency is programmable from 200kHz to 1.6MHz via an external resistor, allowing designers to optimize the tradeoff between efficiency and solution size. An external clock synchronization input enables multiple converters to switch at the same frequency, eliminating beat frequencies in multi-rail systems. The 0.8V +/-1% reference voltage over temperature supports very low output voltages for modern processors and FPGAs. The power-good (PG) output monitors both undervoltage and overvoltage conditions and can be used for power sequencing. The adjustable soft-start controls the output voltage ramp rate, and monotonic startup into pre-biased outputs prevents reverse current during power sequencing. Cycle-by-cycle current limiting on the high-side FET and low-side current limiting protect against overload conditions.

The TPS54620RHLR operates as a synchronous buck converter using current-mode control. Key subsystems include: (1) Current-Mode Control – the inner current loop (inductor current) is closed around the PWM comparator; the error amplifier output (COMP pin) sets the peak inductor current; when the sensed current reaches the COMP level, the high-side FET turns off; this provides inherent cycle-by-cycle current limiting and simplified loop compensation; (2) Integrated MOSFETs – the 26mOhm high-side MOSFET connects VIN to SW and the 19mOhm low-side MOSFET connects SW to GND; the low RDS(on) values minimize conduction losses (P = I^2 x RDS(on)); the separate PVIN pin allows the high-side FET to be powered from a different source than the control logic; (3) Frequency Programming – an external resistor from the RT/CLK pin to GND sets the switching frequency; higher frequencies reduce inductor size but increase switching losses; the RT/CLK pin also accepts an external clock for synchronization; (4) Soft-Start – the SS/TR pin ramps the reference voltage from 0V to 0.8V; an external capacitor sets the ramp time; this limits inrush current during startup; if the output is pre-biased, the converter starts in diode emulation mode until the soft-start voltage exceeds the feedback voltage; (5) Power-Good – the PG pin is an open-drain output that goes high-impedance when VOUT is within the specified window (typically 91-109% of target); UV and OV thresholds provide bidirectional monitoring.

• FPGA core power: 5V or 12V to 1.0V at 6A for high-end FPGA core rail with 0.8V reference
• Processor rail: 12V to 1.8V DDR3 supply at 6A with PG output for power sequencing
• Multi-rail system: synchronized 3x TPS54620 at 500kHz for core, I/O, and memory rails
• Networking blade: 12V intermediate bus to 3.3V at 6A with 1.6MHz for compact solution