ADG719BRMZ

The ADG719BRMZ is a high-performance single-pole double-throw (SPDT) analog switch from Analog Devices, fabricated on an advanced submicron CMOS process that delivers an excellent combination of low on-resistance, high bandwidth, fast switching speed, and ultralow power consumption. As a member of the ADG7xx family of low-voltage CMOS switches, the ADG719 is designed for single-supply operation from 1.8V to 5.5V, making it well-suited for battery-powered portable instruments as well as modern low-voltage signal chain designs using 3.3V or 1.8V supplies. The switch conducts equally well in both directions when on and supports rail-to-rail analog signals, meaning the input signal can range from 0V all the way to VDD without degradation of on-resistance performance. The break-before-make switching ensures that when switching between the two channels, the previously selected channel turns off before the new channel turns on, preventing momentary shorts that could cause glitches or damage to upstream circuitry. With -3dB bandwidth exceeding 200 MHz, the ADG719 is capable of switching high-frequency analog signals including RF, video, and fast data signals. The CMOS construction provides several key advantages: extremely low power consumption (less than 1 microwatt), low leakage currents at the nanoamp level, and TTL/CMOS compatible digital inputs that interface directly with standard logic families. The ADG719BRMZ specifically is the B-grade industrial temperature version, specified over the full -40C to +125C temperature range and packaged in an 8-lead MSOP (mini small-outline package) with RoHS-compliant matte tin lead finish (indicated by the Z suffix). For higher reliability requirements, an enhanced product version (ADG719-EP) is available with AQEC qualification and controlled manufacturing baseline for defense and aerospace applications.

The ADG719BRMZ is a CMOS analog switch that uses complementary MOS transistors (both NMOS and PMOS) connected in parallel as the switching element between the source and drain terminals. When the switch is turned on by applying the appropriate logic level to the control input, both the NMOS and PMOS transistors conduct, creating a low-resistance path between the source and drain terminals. The parallel NMOS/PMOS architecture is what enables rail-to-rail operation: at low signal voltages near ground, the PMOS transistor provides most of the conduction; at high signal voltages near VDD, the NMOS transistor dominates; and in the middle of the range, both transistors contribute. This ensures that the on-resistance remains relatively flat across the entire input signal range, which is why the on-resistance flatness specification (0.75 ohm typical at 5V) is so low. When the switch is turned off, both transistors are cut off, leaving only the leakage current of the reverse-biased PN junctions, which is at the nanoamp level. The break-before-make timing ensures that during a switching transition, there is a brief period (minimum 1 ns, typical 8 ns) when both channels are off before the new channel turns on. This prevents both channels from being simultaneously on, which would create a momentary short between the two source terminals. The digital control input is compatible with both TTL and CMOS logic levels, and the input current is minimal. Because the switch is constructed from CMOS transistors, it draws virtually no quiescent current from the supply when in a static state, resulting in the ultralow power consumption characteristic of CMOS switches.

• Analog input multiplexing for data acquisition systems
• Sample-and-hold circuit input switching
• Audio signal routing in mixers, amplifiers, and audio equipment
• Video switching and routing in video distribution and display systems
• RF signal path switching in communication equipment
• Battery-powered portable test and measurement instruments
• ADC input channel selection and front-end signal conditioning
• DAC output switching and calibration path routing
• Industrial process control analog signal routing
• Communication systems signal path configuration