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IM4G16D3FDBG-107I

4Gb DDR3L SDRAM, 256Mx16, DDR3-1866 CL13, 1.35V/1.5V, -40 to 95C, 96-FBGA

6506

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Pieza del fabricante：

IM4G16D3FDBG-107I

Paquete：

96-FBGA (7.5x13.5mm)

Descripción

Productos

The Intelligent Memory IM4G16D3FDBG-107I is a 4 Gbit (256M x 16) DDR3L SDRAM operating at 933 MHz clock frequency (DDR3-1866) with CL13 latency. It supports both 1.35 V and 1.5 V operation and is rated for industrial temperature range.

Especificaciones

Densidad	4 Gbit (512 MB)
Organization	256M x 16
Speed	DDR3-1866 (933 MHz)
Latencia CAS	CL13
Tensión de alimentación	1.283 V to 1.45 V (DDR3L/DDR3)
Temperatura de funcionamiento	-40°C to +95°C
Paquete	96-FBGA (7.5×13.5mm)

Características

DDR3L 1.35 V / DDR3 1.5 V dual-voltage support
On-Die Termination (ODT)
Write Leveling support
Programmable CAS latency and burst length
Auto-refresh and self-refresh modes
RoHS3 compliant

Aplicaciones

Telecom and networking equipment
Switches and routers
Network storage systems
Industrial computing
Automotive infotainment

Introducción del producto:IM4G16D3FDBG-107I Presentación del producto

The IM4G16D3FDBG-107I from Intelligent Memory is a 4 Gbit DDR3L SDRAM organized as 256M x 16 bits. It operates at DDR3-1866 speed grade (933 MHz clock) with CL13-tRCD13-tRP13 timing. The device supports dual-voltage operation at both 1.35 V (DDR3L) and 1.5 V (DDR3), providing flexibility for various system designs. The industrial temperature grade (-40°C to +95°C) makes it suitable for harsh environments.

Principio de funcionamiento:IM4G16D3FDBG-107I Principio de funcionamiento

The IM4G16D3FDBG-107I is a double data rate synchronous dynamic random-access memory that transfers data on both the rising and falling edges of the clock signal. It uses an 8n-prefetch architecture to achieve high bandwidth. On-Die Termination (ODT) eliminates the need for external termination resistors on the data bus. Write leveling compensates for clock-to-strobe skew in multi-DIMM systems. The device supports programmable CAS latency, additive latency, and burst length for system timing optimization.

Descripción de la clavija:IM4G16D3FDBG-107I Definición y funciones de las clavijas

Grupo Pin	Nombre	Tipo	Descripción
A0-A14	Address	Entrada	Row/column address bus
DQ0-DQ15	Data	E/S	16-bit data bus
BA0-BA2	Bank	Entrada	Bank address
CLK,CLK_n	Reloj	Entrada	Differential clock
CKE	Controlar	Entrada	Clock enable
CS_n	Controlar	Entrada	Chip select
VDD/VDDQ	Potencia	Potencia	Core and I/O supply