NCF3320EHN

The NCF3320EHN is a highly integrated NFC Forum Type 2 Tag IC with dual host interfaces (I²C and SPI) from NXP Semiconductors. This device bridges the gap between NFC RF communication and digital host systems, enabling dynamic NFC tag applications where data can be accessed both wirelessly via NFC and locally through a host microcontroller. Building on NXP’s MIFARE Ultralight and NTAG product line heritage, the NCF3320 adds full host interface capability, making it suitable for a wide range of connected applications. The device features 1.5KB of user EEPROM memory organized into 48 sectors of 32 bytes each. The memory can be accessed both through the NFC RF interface (ISO/IEC 14443 Type A at 13.56 MHz) and through the host interfaces (I²C up to 3.4 MHz or SPI up to 10 MHz). Arbitration logic handles concurrent access attempts, ensuring data integrity. A key feature is energy harvesting, where the device can derive operating power from the NFC RF field, enabling operation even when the host system is powered off. This allows data to be read or written to the tag without needing the host to be active. The RF field detect (FD) pin can be used to wake up the host system when an NFC reader is present. Security features include password-protected memory access and an originality signature based on AES, which can be used to authenticate the device and prevent counterfeiting. The NCF3320 also supports Fast Transfer Mode (FTM) for high-speed data exchange between the RF and host interfaces.

The NCF3320EHN operates as a dual-interface NFC tag controller, bridging RF NFC communication with digital host interfaces. Its operation involves several key functional blocks: 1) RF Analog Front-End (AFE): The NFC antenna connects to the RF pins, where an internal matching network and rectifier circuit extracts both the RF data signal and operating power from the 13.56 MHz NFC field. The AFE demodulates the incoming RF signal and modulates the response back to the reader. Energy harvesting circuitry can provide power to the device from the RF field when host power is unavailable. 2) Digital Protocol Engine: The digital logic implements the ISO/IEC 14443 Type A protocol stack and NFC Forum Type 2 Tag command set. It handles anti-collision, authentication, and memory access commands from the NFC reader. 3) EEPROM Memory Array: The 1.5KB of EEPROM stores the tag data. The memory is organized in pages/sectors with configurable access permissions. Password protection can restrict read/write access to certain memory areas. 4) Host Interface (I²C/SPI): The host microcontroller communicates with the NCF3320 through either I²C or SPI interface. The host can read and write EEPROM memory, configure device settings, and receive interrupt notifications. 5) Arbitration Logic: When both the RF interface and host interface attempt to access memory simultaneously, the arbitration logic manages access to prevent data corruption. 6) Power Management: The device can be powered from the host supply (VCC) or from harvested RF energy. An internal power management unit automatically selects the appropriate power source and manages sleep/wake modes. 7) Field Detect and Interrupt: The FD (Field Detect) pin signals when an NFC RF field is present. The INT pin can be programmed to generate interrupts for various events, enabling event-driven host operation. 8) Security Engine: The AES-based security engine generates and verifies originality signatures, enabling host-side verification of the tag’s authenticity to prevent counterfeiting.

• IoT smart sensor nodes with NFC configuration and data readout
• Wearable devices for NFC pairing and data exchange
• Bluetooth/Wi-Fi easy pairing (just tap to connect)
• Industrial asset tracking with dynamic data logging
• Medical device authentication and patient data exchange
• Smart home devices with NFC commissioning
• Automotive NFC applications (key fobs, infotainment pairing)
• Authentication and anti-counterfeiting for consumer products