PA7128J

The PA7128J is a 128-macrocell Complex Programmable Logic Device (CPLD) designed for high-performance digital logic applications. Built on EEPROM non-volatile technology, it offers the predictable timing and instant-on characteristics inherent to CPLD architectures, making it an excellent choice for glue logic, bus bridging, and control plane applications. The device is organized as 8 Logic Array Blocks (LABs), each containing 16 macrocells, interconnected through a programmable global routing matrix. Each macrocell features four product terms with programmable steering, allowing the allocation of additional product terms to specific macrocells when needed. With a pin-to-pin propagation delay of 7.5ns and counter frequencies up to 178MHz, it supports high-speed system designs. The device supports in-system programming (ISP) through an IEEE 1149.1 JTAG interface, enabling programming and reconfiguration after the device is mounted on the PCB. Each I/O pin features individually programmable output enable, slew rate control, and registered/combinatorial output options. The 84-pin PLCC package provides a robust through-hole form factor with up to 100 available user I/O pins. The PA7128J is suitable for a wide range of applications including bus interfacing, memory control, state machine design, and general-purpose logic consolidation in industrial, telecom, and computing systems.

The PA7128J CPLD operates on the principle of multiple PLD-like logic blocks interconnected through a programmable routing matrix, all implemented with non-volatile EEPROM configuration memory. The architecture consists of three main components: Logic Array Blocks (LABs), a Global Routing Pool (GRP), and I/O Control Blocks. Each of the 8 LABs contains 16 macrocells, each with its own AND array, OR gate, and flip-flop. Within a LAB, 16 macrocells share a common set of input signals from the global routing pool. Each macrocell has four dedicated product terms, with a product term allocator that can redistribute product terms between adjacent macrocells for designs requiring more logic per output. The macrocell flip-flop can be configured as D, T, JK, or SR type, or bypassed entirely for combinatorial operation. The Global Routing Pool (GRP) is a fully connected switching matrix that routes signals between LABs and between LABs and I/O pins. All signals originating from any macrocell output or any I/O pin can be routed to any LAB input through the GRP, providing high routability with predictable delay. I/O pins can be configured as inputs, outputs, or bidirectional signals, with individual output enable control. The JTAG boundary scan interface (IEEE 1149.1) serves dual purposes: it provides boundary scan testing capability for board-level testing, and it enables in-system programming of the EEPROM configuration memory. Because configuration is stored in non-volatile EEPROM cells, the device is instant-on at power-up — no configuration download is required, unlike SRAM-based FPGAs. The EEPROM cells can be reprogrammed at least 10,000 times with data retention guaranteed for 20 years.

• Complex glue logic consolidation
• Bus interface and protocol bridging
• Microprocessor peripheral control
• Memory controller and timing logic
• High-speed state machine design
• Telecom line card processing
• Industrial automation controllers
• Automated test equipment