Product Overview
The TDA10046HT is a single-chip DVB-T channel decoder from NXP Semiconductors (originally Philips Semiconductors), delivering a complete COFDM demodulation solution for digital terrestrial television reception. Fully compliant with ETS 300-744 DVB-T standard, it supports both 2K and 8K transmission modes with all modulation schemes including QPSK, 16QAM, and 64QAM. The device integrates a 10-bit ADC, dual AGC loops, digital adjacent channel filtering, FFT demodulation, channel estimation and equalization, error correction (FEC), and transport stream output in a single TQFP64 package. Fabricated in 0.18 µm CMOS technology, it consumes only 450 mW while providing industry-leading reception performance through advanced features such as adaptive echo cancellation, the proprietary ‘Pulse Killer’ impulsive noise reduction algorithm, and fast channel scanning. Both parallel and serial transport stream interfaces are provided simultaneously, enabling flexible system integration with MPEG decoders and other downstream processing devices.
Key Specifications
| Standard Compliance | ETSI EN 300 744 (DVB-T) |
| Transmission Modes | 2K and 8K COFDM |
| Modulation | QPSK, 16QAM, 64QAM |
| Guard Intervals | 1/32, 1/16, 1/8, 1/4 |
| Code Rates | 1/2, 2/3, 3/4, 5/6, 7/8 |
| Analog Input | 1st or 2nd IF (10-bit on-chip ADC) |
| AGC | Dual loop (IF + RF), programmable takeover point |
| Transport Stream | Parallel (8-bit) + serial (tri-state capable) |
| Clock Reference | 4 MHz crystal oscillator |
| Control Interface | I2C-bus |
| GPIO | 4 pins with ΣΔ modulator |
| I/O Voltage | 5 V tolerant |
| Power Consumption | 450 mW typical |
| Technology | 0.18 µm CMOS |
| Operating Temperature | 0°C to +70°C |
| Package | TQFP-64 (10 x 10 mm) |
Features
- 2K and 8K COFDM demodulator, fully ETS 300-744 compliant
- On-chip 10-bit ADC and PLL for 1st/2nd IF input
- Dual AGC loop (IF + RF) with programmable takeover point
- Adjacent channel digital filtering (only one SAW filter required)
- Automatic frequency offset detection (±1, 2, 3 standard offsets)
- Dynamic FFT window positioning and adaptive echo equalization
- ‘Pulse Killer’ algorithm for impulsive noise reduction
- DSP-based synchronization with firmware upgrade capability
- Ultra-fast UHF/VHF band scanning
- Tri-state parallel and serial transport stream interfaces
- 4 GPIO pins with ΣΔ modulator
- I2C-bus control interface
- 5 V tolerant I/O pins
- Low power consumption: 450 mW
- TQFP64 package, 0.18 µm CMOS technology
Applications
- Integrated digital televisions (iDTV)
- Digital terrestrial set-top boxes (STB)
- Personal video recorders (PVR) with DVB-T reception
- PC TV cards and USB TV tuner adapters
- Portable and handheld TV devices
- Automotive digital TV receivers
- DVB-T over IP gateways and streaming
- Digital signage and public information displays
- Education and test equipment for DVB-T